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Description: 描述了有关矩形编码的verilog语言,非常适合模拟仿真
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Size: 2515 |
Author: zsb |
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Description: 用于FPGA的Z变化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。
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Size: 7571 |
Author: caesar |
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Description: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim
验证,文件中包含TESTBENCH ,直接可用
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Size: 15401328 |
Author: alison |
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Description: 一个 16×8bit 的ROM程序包括程序的初始化。-A 16 × 8bit the ROM initialization procedures, including procedures.
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Size: 3072 |
Author: h13978699183 |
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Description: 描述了有关矩形编码的verilog语言,非常适合模拟仿真-Description of the rectangular coding Verilog language, very suitable for simulation
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Size: 2048 |
Author: zsb |
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Description: 用于FPGA的Z变化算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Platform: |
Size: 7168 |
Author: caesar |
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Description: altera fpga verilog 设计的基于查找表的DCT程序及zigzag扫描程序,已经过matlab 和modelsim
验证,文件中包含TESTBENCH ,直接可用-altera fpga verilog design table DCT-based search procedures and zigzag scanning procedures, and ModelSim matlab has been verified, the document contains TESTBENCH, directly available
Platform: |
Size: 15400960 |
Author: alison |
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