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Description: X-HDL软件是可以智能地实现vhdl<->verilog之间的相互转换的软件，不仅仅是语法转换，而是使用了hdl技术。这是该软件x-hdl3.2.55的license注册补丁，非常难得。
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Size: 5140 |
Author: 黄灿武 |
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Description: 一些c程序，象棋之马踏棋盘、把算术表达式转化未逆波兰表达式、保龄球计分规则算法、可进行多达50位的大整数运算（＋X）、铁路调度算法，演示了堆栈的基本用法-Some c procedures, horse riding chess board, the arithmetic expressions are not translated into Reverse Polish expression, bowling scoring rules algorithm, can be as many as 50 large integer calculations ( X), the railway scheduling algorithm, demonstrated the basic stack Usage
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Size: 4096 |
Author: 站长 |
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Description: 指数平滑法预测数据 输入: k--平滑周期 * n--原始数据个数 * m--预测步数 * alfa--加权系数 * x--指向原始数据数组指针 * 输出: s1--返回值为指向一次平滑结果数组指针 * s2--返回值为指向二次指数平滑结果数组指针 * s3--返回值为指向三次指数平滑结果数组指针 * xx--返回值为指向预测结果数组指针-exponential smoothing forecast data entry : k-- smoothing cycle* n-- raw data Number* m-- forecast steps* alfa-- weighting* x-- at the raw data array pointer output : s1-- return value to a point meeting smoothing results array pointer* s2-- return value to the point second exponential smoothing results array pointer* s3-- return value to point to three exponential smoothing results array pointer* xx-- return value to point to the results of forecasts array pointer
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Size: 1024 |
Author: 浣熊 |
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Description: 二维卷积运算之C语言实现
若x为N1*M1的二维信号，y为N2*M2的二维信号，则卷积为(N1+N2-1)*(M1+M2-1)的信号-2D convolution operators on C language if x N1* M1 to the two-dimensional signal y* M2 N2 for the two-dimensional signal, convolution (N1 N2-1)* (M1 M2- 1) signal
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Size: 3072 |
Author: 劉昱楓 |
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Description: VHDL和Verilog代码互转工具,对EDA工程人员会有很大的帮助.-VHDL and Verilog code referrals tools, EDA staff to be very helpful.
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Size: 3962880 |
Author: 张华 |
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Description: VHDL与VerilogHDL语言之间相互转换-VHDL language and VerilogHDL conversion between
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Size: 3958784 |
Author: 高 |
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Description: 对任意给定的文法G 构造LR(1)
项目集规范族，其中要实现CLOSURE(I)、GO(I,X)、FIRST 集合等。在此基础上，
构造了LR（1）分析表。然后对输入的句子进行语法分析，给出接受或出错报告。
程序采用文件输入输出方式。其中包括两个输入文件：文法grammar.txt，以及
输入串input.txt；两个输出文件：项目集items.txt 和文法的LR(1)分析表
action_table.txt。由于语法分析的结果只给出接受或错误报告，比较简-For any given grammar G constructed LR (1) itemsets family norms, which in order to achieve CLOSURE (I), GO (I, X), FIRST collections, etc.. On this basis, the structure of the LR (1) analysis table. Then the input sentence for grammatical analysis, given the report to accept or wrong. Procedures for the use of file input and output modalities. Including two input file: grammar grammar.txt, as well as the input strings input.txt two output files: itemsets items.txt and grammar LR (1) analysis table action_table.txt. Since the syntax analysis is given only to accept or error reporting, comparison Jane
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Size: 193536 |
Author: 方方 |
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Description: 在指定区域内用指定颜色绘制椭圆.其中区域定义为:x,y,w,h-In designated areas with the specified color mapping oval. One of the region defined as: x, y, w, h
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Size: 1024 |
Author: 水中望月 |
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Description: 802.1x认证客户端，上网认证，内容审计-802.1x client authentication, Internet authentication, the contents of the audit
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Size: 9675776 |
Author: jiang |
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Description: 2乘8按键扫描程序 4个IO口 74LS164串行数据端 时钟端 两个普通IO口-2 x 8 keypad scanner 4 IO I 74LS164 serial data clock terminal end of two common IO port
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Size: 1024 |
Author: zengxiaoqiang |
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Description:
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Size: 4027392 |
Author: navy |
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Description: 8位乘8位的流水线乘法器，采用Verilog hdl编写-8 x 8-bit pipelined multiplier, used to prepare Verilog hdl
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Size: 1024 |
Author: 江浩 |
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Description:
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Size: 59392 |
Author: 王山 |
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Description: 5位的操作数X和Y输入后暂存在寄存器A和B中，两位的操作控制码control暂存在寄存器C中，按照control码的不同，分布实现下列操作：
00控制X+Y
01控制X-Y
10控制X and Y
11控制 X xor Y
运算结果暂存在寄存器D中，然后输出。
-5 of the operand X and Y after the temporary importation of A and B in the register, the two operational control code register C in temporary control, in accordance with the control code is different from the distribution of the realization of the following steps: 00 control X+ Y01 control of X- Y10 control X and Y11 control X xor Y computing the results of temporary storage in the register D, and then output.
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Size: 407552 |
Author: ALEX |
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Description: 课程设计中首先采用Ising model的思想建立一个二维的模型，然后利用重要性抽样和Monte Carlo方法及其思想模拟铁磁-顺磁相变过程。计算了顺磁物质的能量平均值Ev、热容Cv、磁化强度M及磁化率X的值，进而研究Ev、Cv、M、X与温度T的变化关系并绘制成Ev-T图、Cv-T图、M-T图、X-T图，得出顺磁物质的内能随着温度的升高先增大而后趋于稳定值；热容Cv、磁化率X随着温度的升高先增大后减小；磁化强度M在转变温度Tc处迅速减小为零，找出铁磁相变的转变温度Tc大约为2.35-First of all, curriculum design idea of the Ising model used to establish a two-dimensional model, the importance of sampling and then use Monte Carlo simulation methods and their idea of ferromagnetic- paramagnetic phase transition process. Paramagnetic material calculated average energy Ev, heat capacity Cv, magnetization M and susceptibility X value, and then study Ev, Cv, M, X and temperature changes in the relationship between T and plotted into Ev-T map, Cv- T diagram, MT map, XT maps drawn paramagnetic material can be increased as the temperature increased and then stabilized value heat capacity Cv, magnetic susceptibility X as the temperature increases after the first minus small magnetization M in the transition temperature Tc decreases rapidly to zero Department to identify ferromagnetic phase transition around the transition temperature Tc for 2.35
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Size: 1553408 |
Author: Ellison |
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Description: 设计带进位算术逻辑运算单元，根据74LS181功能表，用Verilog HDL硬件描述语言编程实现ALU181的算术逻辑运算功能，编辑实验原理图，在算术逻辑单元原理图上，将其扩展为带进位的算术逻辑运算单元，对其进行编译，并设计波形对其进行仿真验证，最后下载验证-Design into the digital arithmetic logic operation unit, in accordance with menu 74LS181 with Verilog HDL hardware description language programming ALU181 function arithmetic logic operations, editing Experimental schematic diagram, in the Arithmetic Logic Unit schematic diagram on its expansion into the spaces for arithmetic logic operation unit, its compiler, and the design of their simulation waveforms, and finally download the verification
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Size: 667648 |
Author: 623902748 |
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Description: 最小化l1范数的Matlab代码。求解模型为：
min lambda*|x|_1+||A*x-y||_2。其中，|x|_1表示x的1-范数，||*||_2表示2-范数。该模型在稀疏成分分析、压缩传感器等领域有广泛的用途。- l1-Regularized Least Squares Problem Solver
l1_ls solves problems of the following form:
minimize ||A*x-y||^2+ lambda*sum|x_i|,
where A and y are problem data and x is variable (described below).
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Size: 3072 |
Author: 云上 |
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Description: 第十章的代码。
本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示-Chapter X code. This book by more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of additions device/counters, multipliers/dividers, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and the results demonstrate
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Size: 6872064 |
Author: xiao |
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Description: vhdl和Verilog HDL相互转换的软件，很难找的一款-vhdl and Verilog HDL mutual conversion software, very difficult to find a
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Size: 3963904 |
Author: kenshin |
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Description: 一款可以在verilog和VHDL之间互换的工具，经测试，暂无bug-A verilog and VHDL can be exchanged between the tools, tested, no bug
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Size: 3962880 |
Author: 邵文熙 |
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