Description: Xilinx公司 Virtex4 FPGA官方评估板的电路原理图和相应的PCB文件。是Virtex FPGA硬件电路设计的典范参考设计。其中，PCB文件是PADS格式。-Xilinx company official Virtex4 FPGA evaluation board circuit schematic diagram and the corresponding PCB document. Virtex FPGA is the hardware circuit design model for reference design. Which, PCB document format PADS. Platform: |
Size: 1281024 |
Author:程宣 |
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Description: 本应用指南描述了在 Virtex™ -4 XC4VLX25 FF668 -10C 器件中实现的 DDR SDRAM 控制器。该实现运用了直接时钟控制技术来实现数据采集，并采用自动校准电路来调整数据线上的延迟。-This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay. Platform: |
Size: 54272 |
Author:syf |
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Description: Data recovery allows a receiver to extract embedded clock data from an incoming data stream.
The receiver usually extracts the data from the incoming clock/data stream and then moves this
data into a separate clock domain. Sometimes, the receiver’s clock is also used for onward data
transmission. The circuit described in this application note provides a partial solution at data
rates up to 160 Mb/s in a Virtex™ -E -7 device and a Spartan™ -IIE -6 device, up to 320 Mb/s for
a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro -6 device.
The solution is partial in the sense that no clock is actually recovered, but the data arriving is
fully extracted. The speed is limited by the maximum frequency that can be accepted by the
Data Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock,
and another clock shifted by 90 degrees. Platform: |
Size: 68608 |
Author:jia |
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