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[Other resource] DSP做的视频处理系统中FIFO问题解答

Description: DSP做的视频处理系统中FIFO问题解答-DSP video processing system FIFO Questions
Platform: | Size: 3223 | Author: 陈旭 | Hits:

[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A / D chip to control the collection, image data are stored in synchronous FIFO - AL422B
Platform: | Size: 1151 | Author: 古韦剑 | Hits:

[Software Engineering] design-flow-speeding-up-dsp

Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
Platform: | Size: 2837459 | Author: sdfafaf | Hits:

[DSP program] DSP做的视频处理系统中FIFO问题解答

Description: DSP做的视频处理系统中FIFO问题解答-DSP video processing system FIFO Questions
Platform: | Size: 3072 | Author: 陈旭 | Hits:

[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: | Size: 1024 | Author: 古韦剑 | Hits:

[Software Engineering] design-flow-speeding-up-dsp

Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
Platform: | Size: 2837504 | Author: sdfafaf | Hits:

[Software Engineering] fifo3.pdf

Description: 重点介绍了DSP与FIFO的数据传输、DSP与USB的接口电路。解决了一般情况下系统无法做到的用线阵CCD实现二维图像信号复原的问题 -focus on the DSP and FIFO data transmission, DSP and USB interface circuit. Solve the system under normal circumstances can not do in line with two-dimensional CCD image signals of recovery
Platform: | Size: 134144 | Author: 权溪 | Hits:

[VHDL-FPGA-Verilog] video_fifo

Description: 有关视频方面的fifo设计,vhdl编写-Fifo on the video aspects of the design, vhdl prepared
Platform: | Size: 2048 | Author: 曾工 | Hits:

[USB develop] firmware

Description: CY7C68013A传输视频数据时的FIRMWARE，使使用SLAVE FIFO模式-CY7C68013A video data at the time of transmission FIRMWARE, so that the use of SLAVE FIFO mode
Platform: | Size: 163840 | Author: emma | Hits:

[DSP program] sprp181_DM642_FPGA_HardDisk.pdf.tar

Description: DM642 接硬盘的方案，利用FPGA作FIFO缓冲，达到数据/图像/视频的实时高速写入。-DM642 access the hard disk of the program, the use of FPGA for FIFO buffer to data/images/video real-time high-speed write.
Platform: | Size: 2846720 | Author: 李东平 | Hits:

[Special Effects] video_process_base_on_DSPandFPGA

Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型 化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了 三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
Platform: | Size: 546816 | Author: John | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] xapp460

Description: 利用FPGA实现TMDS接口标准，可用于DVI以及HDMI接口的FPGA实现（含文档）-Video Connectivity Using TMDS I/O in Spartan-3A FPGAs
Platform: | Size: 1594368 | Author: wicky | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 一种用于数字视频信号处理的嵌入式FIFO-Signal processing for digital video embedded FIFO
Platform: | Size: 267264 | Author: 李涛 | Hits:

[Other] al422b

Description: The AL422B is a First-In-First-Output (FIFO) video frame memory used to buffer audio/video/graphic data for digital processing
Platform: | Size: 31744 | Author: wl | Hits:

[Program doc] fifovideo

Description: 里面用c语言写的fifo摄像头资料程序和一些文档,说明如何使用fifo摄像头-fifo video material with c language
Platform: | Size: 3654656 | Author: gaoxinglong | Hits:

[Linux-Unix] linux_fifo

Description: 嵌入式linux下fifo程序实现，用于通信，音视频传输缓存。-The embedded Linux FIFO program，For communication, audio and video transmission cache
Platform: | Size: 1024 | Author: 电子通 | Hits:

[Embeded-SCM Develop] AL422B

Description: AL422B是一种视频帧存储器，存储容量为384k×8bits，存储器结构为先进先出（FIFO），其接口非常简单。下面来介绍它的性能特点及应用领域-AL422B is a video frame memory, storage capacity of 384k × 8bits, memory structure FIFO (FIFO), its interface is very simple. Here to introduce its performance characteristics and applications
Platform: | Size: 2048 | Author: yang | Hits:

[VHDL-FPGA-Verilog] FIFOonFPGAtoUSB

Description: 这个一个基于FPGA的FIFO的传输资料，可以用在USB的传输上，里面有视频有源代码，还有估计的设计，相关的文档说明等等。-The transmission of a data FIFO of FPGA-based, can be used on USB transmission, which has a video source code, as well as estimates of design, related documentation, and so on.
Platform: | Size: 12653568 | Author: jav | Hits:

[Windows Develop] [EAHub]Forex-Fury-V3

Description: 与NFA，FIFO，MT4和MT5 Build 600+兼容 经过测试和验证的设置（始终在开发中的新设置）免费 跌幅低于20％的低风险交易策略 ECN支持 有效的资金管理以确保可持续增长 适合多对 可与任何MT4 / MT5交易经纪商合作 多个过滤器，以避免恶劣的市场条件 轻松的5分钟安装以及完整的指南和视频(Compatible with NFA, FIFO, MT4 and MT5 build 600 + Tested and validated settings (always new settings in development) are free of charge Low risk trading strategy with a drop of less than 20% ECN support Effective fund management to ensure sustainable growth Suitable for many pairs Can cooperate with any MT4 / MT5 trading broker Multiple filters to avoid harsh market conditions Easy 5-minute installation with complete guide and video)
Platform: | Size: 866304 | Author: ESON1102 | Hits:

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