Search - vhdl miaobiao

[VHDL-FPGA-Verilog] miaobiao

Description: 完整的的倒计时秒表设计（指示带闪烁）ＶＨＤＬ代码，Ｑuartus 2开发环境，Archive文件，在Ｑuartus2解压即可。-Complete countdown stopwatch design (with flashing instructions) VHDL code, Quartus 2 development environment, Archive documents, in Quartus2 can extract.
Platform: | Size: 113664 | Author: 李淡 | Hits:

[Other] miaobiao

Description: 设计一个可以顺计时和倒计时的秒表。要求计时的范围为00.0S~99.9S，用三位数码管显示。（1）倒计时：通过小键盘可以实现设定计时时间（以秒为单位，最大计时时间为99.9秒）。通过键盘实现计时开始、计时结束。当所设定的倒计时间到达00.0S后，自动停止倒计时，同时响铃。（2）顺计时：初始值为00.0S，通过键盘实现开始计时和结束计时功能。计时结束后，显示记录的时间。（3）用三个发光二极管正确显示以下状态：倒计时状态、顺计时状态、待机状态。（4）每当接收到有效按键时，蜂鸣器发出提示声。
Platform: | Size: 208896 | Author: 李亟 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 基于VHDL环境下的秒表设计源代码很好用的-Environment based on VHDL design source code stopwatch good use
Platform: | Size: 1024 | Author: Jim | Hits:

[SCM] miaobiao.RAR

Description: 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Platform: | Size: 33792 | Author: cuipinpin | Hits:

[Other] miaobiao

Description: 体育用记时秒表，显示MS，S,MIN功能-watch
Platform: | Size: 419840 | Author: 李磊 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: VHDL语言实现秒表并在共阴数码管上动态显示十进制数值-VHDL language stopwatch and digital control on a total of negative dynamic display decimal values
Platform: | Size: 53248 | Author: 高天天 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表功能，自带工程，EDA的设计平台QuartusⅡ-Stopwatch functions, bring their own works
Platform: | Size: 1589248 | Author: huliyan | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 一个精确的到0.01s的时钟源程序，对于初学VHDL理解很有帮助，只给了源程序没有给出仿真波形-An accurate clock source to the 0.01s for the beginner to understand VHDL helpful not only to the simulation waveform of the source
Platform: | Size: 1024 | Author: 小楼 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: VHDL语言实现的秒表设计，具有分秒，计数清零等功能-VHDL language implementation of the stopwatch design, with the minutes and seconds, counting functions such as Clear
Platform: | Size: 316416 | Author: tangchengjiang | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: vhdl实现秒表，功能包括计时、冻结时间显示、暂停-vhdl implementation stopwatch functions, including time, freezing time display, pause
Platform: | Size: 2148352 | Author: nuandong | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用VHDL实现的秒表功能，包括分频器，动态显示模块-VHDL implementation with stopwatch functions, including crossover, dynamic display module
Platform: | Size: 332800 | Author: miaoxiaohu | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用verilog VHDL描写的秒表程序，可以显示百分秒，秒和分。-Verilog VHDL with the description of a stopwatch program, can display the arc, seconds and points.
Platform: | Size: 380928 | Author: 彭全飞 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 实验课编写的vhdl程序，秒表适用！具体功能是开始计时，停止，清零！经实验，完美运行！-Vhdl program written by the Lab, stopwatch applicable! Specific start time, stop, clear! The experiment, a perfect run!
Platform: | Size: 1024 | Author: | Hits:

[Com Port] miaobiao

Description: 秒表应用VHDL语言设计数字系统，很多设计工作可以在计算机上完成，从而缩短了数字系统的开发时间。我们尝试利用VHDL为开发工具设计数字秒表。秒表的逻辑结构较简单，它主要由十进制计数器、六进制计数器、数据选择器、和显示译码器等组成。在整个秒表中最关键的是如何获得一个精确的100HZ计时脉冲，除此之外，整个秒表还需有一个启动信号和一个清零信号，以便秒表能随意停止及启动。秒表有共有6个输出显示，分别为百分之一秒、十分之一秒、秒、十秒、分、十分，所以共有6个计数器与之相对应，6个计数器的输出全都为BCD码输出，这样便与同显示译码器连接。-simple miaobiao
Platform: | Size: 2048 | Author: 范增 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 秒表的VHDL语言程序，是实验课上一个课程设计，非常正确，非常好用。-Stopwatch VHDL language program is the experimental class curriculum design, very correct, very easy to use.
Platform: | Size: 7168 | Author: 塚客 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用VHDL语言实现对FPGA的程序编写，实现秒表功能。-Using VHDL FPGA program written stopwatch function.
Platform: | Size: 372736 | Author: 秦丽媛 | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 基于Max+plus2软件的Verilog VHDL语言的按键控制数码管显示秒表-Based on Max+plus2 software Verilog VHDL language button control digital display stopwatch
Platform: | Size: 457728 | Author: lzhf | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用VHDL编写的一个数字钟，可以完成计时功能。-VHDL prepared a digital clock, you can complete the timing function.
Platform: | Size: 630784 | Author: 李鹏飞 | Hits:

[Other] miaobiao

Description: 利用vHdl描述语言实现的60秒秒表。能够实现60秒的计时功能-Use of vHdl description language implementation 60 seconds stopwatch
Platform: | Size: 1024 | Author: wuqiangsheng | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: EDA--miaobiao design-vhdl----miaobiao design
Platform: | Size: 1286144 | Author: 代林 | Hits:

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[VHDL-FPGA-Verilog] miaobiao

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[SCM] miaobiao.RAR

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[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

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[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[Com Port] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

[VHDL-FPGA-Verilog] miaobiao

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[VHDL-FPGA-Verilog] miaobiao

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