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[VHDL-FPGA-Veriloghdlc

Description: HDLC通信模块发送接收模块VHDL源码-HDLC communication module to send receiver module VHDL source code
Platform: | Size: 3072 | Author: ditto | Hits:

[Embeded-SCM DevelopHDLC

Description: hdlc帧接收器 包含文件: 设计代码 测试代码 综合脚步 说明文档-HDLC frame receiver include file: design code test code Comprehensive documentation footsteps
Platform: | Size: 447488 | Author: wangjie | Hits:

[Embeded-SCM Develophdlc-code

Description: 用硬件描述语言实现HDLC通道的功能,取代HDLC专用芯片-Hardware description language used to achieve the functions of HDLC channel to replace the HDLC ASIC
Platform: | Size: 11264 | Author: zhanghf | Hits:

[Embeded-SCM Develophdlc

Description: hdlc 总线的vhdl 的样例代码。包含代码和说明文档。-hdlc-bus vhdl sample code. Contains code and documentation.
Platform: | Size: 205824 | Author: rensijun | Hits:

[VHDL-FPGA-Veriloghdlc

Description: HDLC协议的VHDL源码。接收和发送模块,以及所用FIFO的IP核(Xilinx公司)。-The code of HDLC protocol.Receive and transmit module is contained.
Platform: | Size: 10240 | Author: wei | Hits:

[Com PortHDLC_VHDL

Description: 用VHDL实现从以太网到并行数据以及从并行数据到以太网的HDLC成帧解帧.附详细代码说明,方便阅读.可方面移植到Altera及Xilinx等厂家芯片,是做基于FPGA的以太网设计的好资料-Achieved using VHDL and parallel data from the Ethernet to parallel data from the HDLC framing solution to Ethernet frames. Attached detailed code instructions, easy to read. Can be ported to Altera and Xilinx areas such as chip manufacturers are doing to FPGA-based very good information network design
Platform: | Size: 11264 | Author: 卓福洲 | Hits:

[VHDL-FPGA-Verilogcore

Description: HDLC core, standalone controller with buffers. vhdl source code
Platform: | Size: 17408 | Author: Hellen | Hits:

[VHDL-FPGA-Veriloghdlc

Description: HDLC code in vhdl working code
Platform: | Size: 39936 | Author: hr | Hits:

[VHDL-FPGA-Veriloghdlc

Description: 这是VHDL语言编写的实现 HDLC通信协议的源代码-This is the HDLC communications protocol source code written in VHDL language
Platform: | Size: 10240 | Author: sean | Hits:

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