Search - vhdl core pci

[VHDL-FPGA-Verilog] PCI_target

Description: VHDL编写的PCI代码,PCI2.2兼容,Xillinx Virtex与Spantan II 优化,33M主频,32位宽度,全目标功能等.-prepared by the PCI VHDL code, PCI2.2 compatible Xillinx Virtex II and Spantan optimized route speed, 32-bit width, the whole objective functions.
Platform: | Size: 844800 | Author: citybus | Hits:

[Other] PCI_Target_ip

Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Platform: | Size: 428032 | Author: zhouhong | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] CPRI

Description:
Platform: | Size: 933888 | Author: 郭坚 | Hits:

[VHDL-FPGA-Verilog] pci_core

Description: pci CORES 从外国网站上弄下来的，大家可以看看啊-pci CORES from foreign web sites get down, we will look at ah
Platform: | Size: 28672 | Author: haitao | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。本PCI_HOST目前支持： 1、对目标PCI_T进行配置； 2、对目标进行单周期读写； 3、可以工作在33MHZ和66MHZ 4、支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[VHDL-FPGA-Verilog] PCI-IPcoreor1k[1]

Description: PCI的ip core，VHDL代码，希望对大家有帮助-PCI-ip core, VHDL code, we hope to help
Platform: | Size: 1064960 | Author: 李明 | Hits:

[VHDL-FPGA-Verilog] pci_core.tar

Description: vhdl 写的 PCI IP核程序，已经过测试-pci ip core
Platform: | Size: 23552 | Author: planet1997 | Hits:

[VHDL-FPGA-Verilog] FPGA_8008

Description: pci pci转local bus总线的应用，使用IPcore alter器件-pci pci convert local bus application,use alter IP core
Platform: | Size: 493568 | Author: robincyh | Hits:

[Embeded-SCM Develop] bijiaoqi

Description: pci 32位的core的实现源代码，我晕阿，实在是不好怎么说阿-pci 32-bit core of the realization of the source code, I fainted Ah, how to say it is not Arab. . . .
Platform: | Size: 30720 | Author: adfdf | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

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[VHDL-FPGA-Verilog] PCI_target

[Other] PCI_Target_ip

[VHDL-FPGA-Verilog] pci_express_crc

[VHDL-FPGA-Verilog] CPRI

[VHDL-FPGA-Verilog] pci_core

[VHDL-FPGA-Verilog] hgb_pci_host

[VHDL-FPGA-Verilog] PCI-IPcoreor1k[1]

[VHDL-FPGA-Verilog] pci_core.tar

[VHDL-FPGA-Verilog] FPGA_8008

[Embeded-SCM Develop] bijiaoqi

[Embeded-SCM Develop] pci.tar

[VHDL-FPGA-Verilog] pciug159

[VHDL-FPGA-Verilog] pci_32tlite_oc

[VHDL-FPGA-Verilog] IPcore

[VHDL-FPGA-Verilog] testbench

[VHDL-FPGA-Verilog] pci_744

[VHDL-FPGA-Verilog] pcixpci_corev702errfix

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