Search - vhdl code for crc

[VHDL-FPGA-Verilog] CRC-Verilog

Description: 此是进行循环冗余效验的Verilog编码，适合多种标准，如CRC16-this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Platform: | Size: 3072 | Author: 藏瑞 | Hits:

[Crack Hack] crc

Description: 此源代码实现了CRC5和CRC16的校验以及校验码的产生，可以直接用于RFID标签数字电路。-This source code CRC5 and realize the CRC16 checksum and the emergence of parity-check codes, RFID tags can be directly used for digital circuits.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] crc

Description: 可以直接用于工程应用的crc校验VHDL编码里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications
Platform: | Size: 90112 | Author: 毋杰 | Hits:

[Crack Hack] crc

Description: CRC码产生器与校验器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset-CRC code generator and calibration program Features: Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
Platform: | Size: 5120 | Author: Alex | Hits:

[VHDL-FPGA-Verilog] ethernet.tar

Description: 以太网的vhdl和verilog代码，供大家学习-Ethernet VHDL and Verilog code for everyone to learn
Platform: | Size: 934912 | Author: sunlee | Hits:

[Crack Hack] CRC

Description: 通过对于模2除法的研究可以得到如下方法： 1．把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2．在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3．如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4．把滑块变量d往后滑动一位。 5．循环步骤（3，4）11次。 6．执行步骤3。 7．得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[Crack Hack] crc16

Description: 16bit CRC for 8bits data
Platform: | Size: 1024 | Author: 苗淼 | Hits:

[VHDL-FPGA-Verilog] crc_8

Description: 用vhdl编写的CRC校验代码，仿真以及下载在板上测试通过-Prepared by the CRC checksum vhdl code, simulation, and download the on-board test
Platform: | Size: 2048 | Author: siubr | Hits:

[source in ebook] crc8

Description: 8bit CRC码生成器vhdl 代码，延时一个周期CRC码有效。-8bit crc code genergator,after delay one clock,crc code valid
Platform: | Size: 1024 | Author: luoda | Hits:

[Communication-Mobile] crc32_4

Description: 实现了crc功能的verilog源程序。可以综合。-verilog code for crc
Platform: | Size: 1024 | Author: tree | Hits:

[Other] venomgen

Description: venomgen - C source code of VHDL code generator for CRC, BCH and RS encoder -venomgen- C source code of VHDL code generator for CRC, BCH and RS encoder * polynomials can be entered via command line * variable bus width * automatic testbench generation
Platform: | Size: 258048 | Author: Michael Lau | Hits:

[VHDL-FPGA-Verilog] PCK_CRC16_D1

Description: CRC源代码，VHDL文件，可供参考，16位的-CRC source code, VHDL files, for reference, 16-bit
Platform: | Size: 1024 | Author: ly | Hits:

[VHDL-FPGA-Verilog] crc-gen

Description: CRC Generator is a command-line application that generates Verilog or VHDL code for CRC of any data width between 1 and 1024 and polynomial width between 1 and 1024. The code is written in C and is cross-platform compatible
Platform: | Size: 60416 | Author: badfox | Hits:

[VHDL-FPGA-Verilog] CRCDecoding

Description: CRC检错程序。只能检错不能纠错。（40,32）的分组码检错，反馈函数：x8+x7+x4+x3+x+1-CRC error detection process. Not only error detection correction. (40,32) and block code error detection, feedback function: x8+ x7+ x4+ x3+ x+1
Platform: | Size: 147456 | Author: 李雪茹 | Hits:

[VHDL-FPGA-Verilog] module-Temperature

Description: DS18B20引脚功能 GND地，DQ数据总线，VDD电源电压 18B20共有三种形式的存储器资源，它们分别是： ROM 只读存储器，用于存放DS18B20ID编码，其前八位是单线系列编码，后面48位是芯片唯一的序列号，最后8位是以上56位的CRC码。DS18B20共64位ROM RAM 数据暂存器，数据掉电后丢失，共9个字节，每个字节8位，第1、2个字节是温度转换后的数据值信息，EEPROM 非易失性记忆体，用于存放长期需要保存的数据，上下限温度报警值和校验数据 -DS18B20 Function GND Ground pin, DQ data bus, VDD supply voltage 18B20 There are three forms of memory resources, they are: ROM read-only memory for storing DS18B20ID coding, the top eight single-family is encoded, followed by 48 is the chip serial number only, over the last eight is 56-bit CRC code. DS18B20 total of 64-bit ROM RAM data store, data loss after power-down, a total of 9 bytes, each byte 8-bit, 1, 2 bytes of temperature data converted value information, EEPROM non-volatile volatile memory for storage of long-term need to preserve data, upper and lower temperature alarm and calibration data
Platform: | Size: 9216 | Author: 袁亚楠 | Hits:

[VHDL-FPGA-Verilog] CRC-8

Description: VHDL code for CRC-8 computing using 32 bit input (parallel)
Platform: | Size: 1024 | Author: stefanovic | Hits:

[VHDL-FPGA-Verilog] CRC

Description: 赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the module features to suit the protocol or application implemented in their system. The user-specified options for each of the configurable features are input parameters to the VHDL code for the modules. The VHDL source files for the CRC modules are coded using generate statements. The modules have two LocalLink interfaces: an upstream interface (US) and a downstream interface (DS)
Platform: | Size: 210944 | Author: 我是谁 | Hits:

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[VHDL-FPGA-Verilog] CRC-Verilog

[Crack Hack] crc

[VHDL-FPGA-Verilog] crc

[Crack Hack] crc

[VHDL-FPGA-Verilog] ethernet.tar

[Crack Hack] CRC

[Crack Hack] crc16

[VHDL-FPGA-Verilog] crc_8

[source in ebook] crc8

[Communication-Mobile] crc32_4

[Other] venomgen

[VHDL-FPGA-Verilog] PCK_CRC16_D1

[VHDL-FPGA-Verilog] crc-gen

[VHDL-FPGA-Verilog] CRCDecoding

[VHDL-FPGA-Verilog] module-Temperature

[VHDL-FPGA-Verilog] CRC-8

[VHDL-FPGA-Verilog] CRC

[VHDL-FPGA-Verilog] crcmodule

[VHDL-FPGA-Verilog] crc16

[VHDL-FPGA-Verilog] P12_CRC

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