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Search - verilog video compression

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[Multimedia program] H263video

Description: H.263的视频压缩算法和测试程序，可以对原始图像和转码后的图像进行比较。开发环境为vc6.0。-H.263 video compression algorithm and testing procedures, the original image and switch codes after the images were compared. Development Environment for vc6.0.
Platform: | Size: 362496 | Author: lh | Hits:

[Multimedia program] dct

Description: Mpeg2视频压缩时进行空间压缩时的离散余弦变换矩阵的verilog实现，采用modelsim验证-Mpeg2 video compression when space compression of discrete cosine transform matrix realize Verilog using ModelSim verification
Platform: | Size: 29696 | Author: mayang | Hits:

[mpeg mp3] entropy_coding

Description: mpeg2视频压缩熵编码，verilog实现，modelsim仿真通过-mpeg2 video compression entropy coding, verilog realize, modelsim simulation through
Platform: | Size: 19456 | Author: mayang | Hits:

[OpenGL program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: yangyanwen | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[Compress-Decompress algrithms] MQdecoder

Description: Verilog HDL 实现的JPEG200的MQ解码-JPEG2000 MQ DECODER BASED ON FPGA， Verilog HDL
Platform: | Size: 1518592 | Author: 林木 | Hits:

[VHDL-FPGA-Verilog] H.264decodeVerilog

Description: 基于FPGA的EDA设计技术，用Verilog硬件设计语言解压缩H.264格式的视频压缩文件。-FPGA-based EDA design, using Verilog hardware design language decompress H.264 video compression format file.
Platform: | Size: 882688 | Author: 吴文 | Hits:

[Graph program] DCT

Description: 用Verilog HDL编写的离散余弦变换，可用于视频图像压缩，并在modelsim SE6.0中仿真通过-Verilog HDL prepared with discrete cosine transform can be used for video image compression, and modelsim SE6.0 simulation through
Platform: | Size: 1024 | Author: shi17395 | Hits:

[VHDL-FPGA-Verilog] H.265视频压缩的FPGA实现

Description: 使用verilog语言实现H.265压缩算法，能够实现实时视频数据的压缩传输(Using Verilog language to realize h.265 compression algorithm can realize the compression and transmission of real-time video data)
Platform: | Size: 14726144 | Author: xiaotaiy | Hits:

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