Search - verilog rom model

[VHDL-FPGA-Verilog] rom

Description: Read-only memory,Verilog code
Platform: | Size: 8192 | Author: leigh lee | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] RTL

Description: verilog编写的关于使用MENTOR的MBISTArchitect进行momery的自测试代码，包含测试算法模型，SRAM,ROM模型-verilog prepared by the use of MBISTArchitect for momery MENTOR self-test code, including test algorithm model, SRAM, ROM model
Platform: | Size: 305152 | Author: | Hits:

[VHDL-FPGA-Verilog] rom

Description: ROM模式的实现机制，基于verilog语言。-Implementation mechanism of ROM model, based on Verilog language.
Platform: | Size: 1024 | Author: mxc | Hits:

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[VHDL-FPGA-Verilog] rom

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

[VHDL-FPGA-Verilog] RTL

[VHDL-FPGA-Verilog] rom

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