Search - verilog convolution

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25437 | Author: 李寧 | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[source in ebook] RSencode

Description: 包含RS（10，8）的verilog源程序，加法器的verilog源程序，卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[VHDL-FPGA-Verilog] Convolution

Description:
Platform: | Size: 104448 | Author: 龚阳 | Hits:

[Other] interleaver

Description: This is a convolutional interleaver code written in verilog, the ram is sram with ram_ncs, ram_nwe, ram_noe characters.
Platform: | Size: 2048 | Author: tomsontiger | Hits:

[VHDL-FPGA-Verilog] baseband_verilog

Description: verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器-verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter
Platform: | Size: 26624 | Author: 刘新 | Hits:

[Communication] conv_vhdl

Description: 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[matlab] Easy-convolution-Verilog-file

Description: convolution code for beginers in the field of communication
Platform: | Size: 106496 | Author: Jacknapes | Hits:

[VHDL-FPGA-Verilog] convcode

Description: 基于Modelsim的卷积码(2,1,7)的Verilog实现，采用直接生成-Modelsim-based convolution code (2,1,7) and Verilog implementation of direct generation
Platform: | Size: 17408 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] viterbi

Description: 维特比译码，卷积编码，verilog编写，2,1,2编码-Victor than decoding, convolution code, verilog write, 2,1,2 coding
Platform: | Size: 2048 | Author: 洪依 | Hits:

[VHDL-FPGA-Verilog] convotion_decode

Description: 用verilog写的卷积码的编码程序以及viterbi译码程序-Use verilog write convolution code coding procedures and viterbi decoding program
Platform: | Size: 35840 | Author: 蔡金峰 | Hits:

[VHDL-FPGA-Verilog] juanji_3_3

Description: 自己写的3*3的高斯卷积模板，用Verilog在ISE上写的-Write your own 3x3 Gaussian convolution mask, using Verilog write on the ISE
Platform: | Size: 3945472 | Author: 刘恒建 | Hits:

[Software Engineering] rs_code

Description: 本文在介绍卷积码原理和描述方式的基础上以1/2卷积码为例重点详细阐述了基于Verilog HDL 的卷积码的编器的设计-This paper introduced the convolution code on the principles and methods described in 1/2 convolutional code as an example focuses elaborated convolution based on Verilog HDL code compiled Design
Platform: | Size: 171008 | Author: tianhongliang | Hits:

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[Compress-Decompress algrithms] jpeg_encoder

[Compress-Decompress algrithms] jpeg_encoder

[Compress-Decompress algrithms] 601792346200732319490634862

[source in ebook] RSencode

[VHDL-FPGA-Verilog] Convolution

[Other] interleaver

[VHDL-FPGA-Verilog] baseband_verilog

[Communication] conv_vhdl

[matlab] Easy-convolution-Verilog-file

[VHDL-FPGA-Verilog] convcode

[VHDL-FPGA-Verilog] viterbi

[VHDL-FPGA-Verilog] convotion_decode

[VHDL-FPGA-Verilog] juanji_3_3

[Software Engineering] rs_code

[Program doc] convolution

[Software Engineering] verilog-2-1-4

[VHDL-FPGA-Verilog] convolution

[VHDL-FPGA-Verilog] convolution

[VHDL-FPGA-Verilog] Convolution

[VHDL-FPGA-Verilog] 卷积码程序verilog

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