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[SCM] 128FFT

Description:
Platform: | Size: 1024 | Author: | Hits:

[Mathimatics-Numerical algorithms] dft

Description: verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module!
Platform: | Size: 1024 | Author: 刘庆 | Hits:

[VHDL-FPGA-Verilog] Rader17.v

Description: DFT Implementation with Rader Algorithm. 17 points DFT verilog implementation design.
Platform: | Size: 2048 | Author: zi | Hits:

[Other] tap_controller

Description: JTAG tap controller, used for DFT(JTAG tap controller verilog version)
Platform: | Size: 1024 | Author: borselin | Hits:

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