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[ELanguage] usb_funct

Description: USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Platform: | Size: 230536 | Author: 王森 | Hits:

[Other resource] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言
Platform: | Size: 975764 | Author: 杨林成 | Hits:

[VHDL-FPGA-Verilog] bfm

Description: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Platform: | Size: 2048 | Author: wyl | Hits:

[ELanguage] usb_funct

Description: USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Platform: | Size: 230400 | Author: 王森 | Hits:

[VHDL-FPGA-Verilog] FT245BM

Description: 这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序，用的是Verilog HDL语言-This is a MAX II CPLD module using USB transmit FT245BM reading and writing process, using Verilog HDL language
Platform: | Size: 975872 | Author: 杨林成 | Hits:

[USB develop] usb20_ipcore_usb_funct

Description: usb的芯片ip core. 用HDL描述，适合asic/fpga人员参考或使用。USB ip core for ASIC/FPGA designers.-usb chips ip core. with HDL description suitable for asic/fpga staff reference or use. USB ip core for ASIC/FPGA designers.
Platform: | Size: 208896 | Author: road | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: fifo用Verilog hdl的实现，这是一个比较常用的源码，文档中有很详细的注释，初学者应该可以看懂。-implementation using Verilog hdl usb, this is a common source, the document had a very detailed notes, beginners should understand.
Platform: | Size: 6144 | Author: zhulyan580086 | Hits:

[VHDL-FPGA-Verilog] USB_FPGA

Description: 基于Cyclone EP3C25的USB与CY60183传递数据的FIFO Verilog HDL源代码（FPGA端程序）-The program is a communication source code about USBCyclone EP3C25 transfering data via FIFO with CY60183 (only FPGA source code(verilog HDL) is included)
Platform: | Size: 1024 | Author: lee | Hits:

[Software Engineering] VERILOGUSB2.0-IP

Description: USB IP核 verilog 语言 完整的use ip核-use ip verilog HDL
Platform: | Size: 588800 | Author: 赵彦选 | Hits:

[ARM-PowerPC-ColdFire-MIPS] FA161-SCH

Description: 联华众科FPGA开发板FA161核心器件为 Altera Cyclone系列FPGA EP1C6，FA161板载有SDRAM，SRAM，FLASH方便制作各种应用，开发板所带资料中包括了上位机与开发板USB通信，上位机与开发板以太网通信，上位机与开发板串口通信例程。FA161板载有USB 1.1，USB 2.0(CY7C68013A)接口，以太网接口(RTL8019AS)。FA161上可以进行HDL程序开发，可以进行nios ii程序开发，可以结合MATLAB制作DSP Builder应用。FA161上可以运行uClinux和Micro C/OS-II实时操作系统。-Lianhua Branch FPGA development board FA161 core device for Altera Cyclone series FPGA EP1C6 FA161 onboard SDRAM, SRAM, FLASH facilitate the production of a variety of applications, including the host computer and the development board development board brought information USB communication, the PCdevelopment board Ethernet communication, the host computer and the development board serial communication routines. The FA161-board have USB 1.1, USB 2.0 (CY7C68013A) interface, Ethernet interface (RTL8019AS). HDL program development, FA161 can be nios ii program development, combination of MATLAB production DSP Builder application. The FA161 can run uClinux and Micro C/OS-II real-time operating system.
Platform: | Size: 2085888 | Author: qchwu | Hits:

[VHDL-FPGA-Verilog] can_exm1_sys

Description: CAN总线的数据采集，FPGA到USB。verilog hdl语言。-CAN bus data acquisition, FPGA to the USB. verilog hdl language.
Platform: | Size: 756736 | Author: xiaolou | Hits:

[VHDL-FPGA-Verilog] CH376

Description: 用VERILOG HDL语言写的usb程序。FPGA芯片用的是ALTERA公司的，编程所用的软件为quartus和nios，USB芯片为CH376.-VERILOG HDL language written with usb program. ALTERA FPGA chip using the company s software program used quartus and nios, USB chip CH376.
Platform: | Size: 6358016 | Author: 周燕 | Hits:

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