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[Other resource] color_bar

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Platform: | Size: 10577 | Author: 石坚 | Hits:

[Other resource] razzle

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.
Platform: | Size: 10635 | Author: 石坚 | Hits:

[CSharp] up3

Description: 本程序为“有向图的遍历及运算”，非常方便使用，希望大家能够喜欢。-the procedures as "directed graph traversal and calculations," is very convenient to use and I hope we can like.
Platform: | Size: 29773 | Author: 苏杰 | Hits:

[Other resource] UP3_CLOCK2

Description: UP3开发板上的时钟控制源代码文件，VHDl编写-degrading development control board clock source documents, prepared VHDl
Platform: | Size: 1074 | Author: xufeng | Hits:

[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43004 | Author: ngzhongsyen | Hits:

[Other resource] UP3_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒，具有闹钟，整点报时， 时间可重新设置等功能，在LCD1602上显示。 绝对推荐，比网上其他类似代码功能要全而且经过验证。
Platform: | Size: 728583 | Author: kehan | Hits:

[Other resource] UP3_CLOCK

Description: 采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。
Platform: | Size: 70369 | Author: 小毛头 | Hits:

[assembly language] clock

Description: 用vhdl开发的up3 clock,可以在up3的led上显示24小时制时分秒
Platform: | Size: 14942 | Author: 李瑶 | Hits:

[Other resource] UP3_RTC_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。最关键的是该代码是直接通过I2C总线来获取UP3开发板上的实时时钟芯片的时间的,当然也可以通过I2C对时钟芯片进行设置.
Platform: | Size: 1367434 | Author: kehan | Hits:

[Other resource] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；
Platform: | Size: 6164686 | Author: Emma | Hits:

[Other resource] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。 实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线 上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。 实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频 率也是由频率字控制的。LCD的驱动原理同上次实验。
Platform: | Size: 1225901 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] color_bar

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[VHDL-FPGA-Verilog] razzle

Description: 使用vhdl语言在altera公司的up3板上产生vga信号，里面有详细的解析和说明，是一个很好的教程。和上一个文件razzle差不多，但是产生的效果不一样。-use of the VHDL language ALTERA company's board up3 have vga signal containing a detailed analysis and explanation is a good guide. And on a razzle almost document, but the effects are not the same.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[CSharp] up3

Description: 本程序为“有向图的遍历及运算”，非常方便使用，希望大家能够喜欢。-the procedures as "directed graph traversal and calculations," is very convenient to use and I hope we can like.
Platform: | Size: 29696 | Author: 苏杰 | Hits:

[VHDL-FPGA-Verilog] UP3_CLOCK2

Description: UP3开发板上的时钟控制源代码文件，VHDl编写-degrading development control board clock source documents, prepared VHDl
Platform: | Size: 1024 | Author: xufeng | Hits:

[VHDL-FPGA-Verilog] UP3_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。 精确到十分之一秒，具有闹钟，整点报时， 时间可重新设置等功能，在LCD1602上显示。 绝对推荐，比网上其他类似代码功能要全而且经过验证。-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified.
Platform: | Size: 728064 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] UP3_CLOCK

Description: 采用vhdl语言编写的UP3开发板电子钟程序。在quartus中编译完成。-Using VHDL language UP3 development board electronic bell procedures. Compiled in the Quartus completed.
Platform: | Size: 69632 | Author: 小毛头 | Hits:

[assembly language] clock

Description: 用vhdl开发的up3 clock,可以在up3的led上显示24小时制时分秒-Developed using VHDL up3 clock, can be led in the up3 display system for 24 hours every minute
Platform: | Size: 14336 | Author: 李瑶 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[Wavelet] DDS

Description: 利用EDA技术和FPGA在UP3开发板上实现直接数字频率综合器的设计。 实验中加入了相位控制字PWORD，用以控制相位偏移量的前四位，将相位偏移量加到ROM地址总线 上，从而引起从ROM中取得的正弦信号的偏移，实现移相信号发生器的移相功能。 实验中还加入了LCD显示功能，通过LCD显示模块器件，用LCD显示正弦信号的频率，所显示的频 率也是由频率字控制的。LCD的驱动原理同上次实验。-The use of EDA technology and FPGA development in the UP3 board direct digital frequency synthesizer design. Experiment by adding a phase control word PWORD, to control the phase offset of the top four will be added to the phase offset ROM address bus, thereby causing ROM obtained from the sinusoidal signal offset, shifted believe realize its phase-shifting function generator. Experiments have also joined the LCD display, LCD display module through the device, with LCD display the frequency of sinusoidal signal, as shown by the frequency of word frequency control. LCD driving principles with the previous experiment.
Platform: | Size: 1225728 | Author: Emma | Hits:
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