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[VHDL-FPGA-Verilogfftinterface

Description: 电赛一等奖作品:音频信号分析仪的FPGA源码,VHDL编写,Quartus7.1综合,ModelSim6.2g se仿真,应用了opencores.org上的开源FFT IP核,加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[Com Portuart

Description: 开源的串口通信程序,用vhdl 编写的,已通过测试,在DE2的开发板上能够运行。-Open source serial communication procedures, prepared by using VHDL, has been tested in the DE2 development board to run.
Platform: | Size: 2048 | Author: caijl88 | Hits:

[VHDL-FPGA-Veriloguart16550_latest[1].tar

Description: 开源UART IP核16550,该IP核兼容16550 UART,具有Modem功能,完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[VHDL-FPGA-Veriloguart-

Description: 通用异步通讯UART的工程文档,ISE打开工程,里面有VERILOG的源代码,可以编译通过-UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
Platform: | Size: 30720 | Author: mike | Hits:

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