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[Com PortUART

Description: 内含有完整的UART代码,包括发送和接受,且有testbench,可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[VHDL-FPGA-VerilogUARTtransmitter

Description: UART Transmitter. VHDL code and its testbench.
Platform: | Size: 2048 | Author: mehmet | Hits:

[VHDL-FPGA-Veriloguart-vhdl-testbench

Description: simple uart vhdl behavioural model (package) vhdl testbench example
Platform: | Size: 2048 | Author: Mark | Hits:

[VHDL-FPGA-VerilogUART

Description: 用VHDL编写实现的UART控制器源码,自带testbench,解压后用ISE打开工程文件即可。-Prepared with the VHDL source code to achieve the UART controller, bring their own testbench, after decompression project file can be opened with the ISE.
Platform: | Size: 25600 | Author: 陈阳 | Hits:

[VHDL-FPGA-Veriloguart2bus_latest.tar

Description: 文档详尽、已验证的UART工程,含有testbench文件。采用VHDL、Verilog语言编写。-Detailed documentation, has proven UART works with testbench file. Using VHDL, Verilog language.
Platform: | Size: 224256 | Author: robin | Hits:

[VHDL-FPGA-Veriloguartlvds

Description: UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
Platform: | Size: 12288 | Author: 毕向伟 | Hits:

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