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Description: spi bootloader详细资料,里面包含C代码和VHDL代码以及testbench以及相关的说明文档,有兴趣的朋友可以下来看看。
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Size: 192895 |
Author: zheng jun |
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Description: I2C bus HDL source and testbench
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Size: 701440 |
Author: liuKe |
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Description: spi bootloader详细资料,里面包含C代码和VHDL代码以及testbench以及相关的说明文档,有兴趣的朋友可以下来看看。-spi bootloader detailed information, which contains C code and VHDL code and Testbench and related documentation, interested friends can see them.
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Size: 192512 |
Author: zheng jun |
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Description: verilog ADPLL file with testbench
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Size: 197632 |
Author: xgh |
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Description: verilog spi file with testbench
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Size: 2934784 |
Author: xgh |
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Description: verilog vcspi file with testbench
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Size: 1944576 |
Author: xgh |
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Description: test bench for spi communication
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Size: 1024 |
Author: Onur |
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Description: SPI协议Verilog HDL程序,内含testbench 文件
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Size: 81920 |
Author: dsahd |
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Description: This a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile and simulate
Platform: |
Size: 9216 |
Author: RutaliMulye |
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Description: MAXII SPI interface with testbench
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Size: 472064 |
Author: xornonop |
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Description: 用VHDL编写的一个SPI主机程序,SPI模块采用最常用的模式0方式(即CPOL=0,CPHA=0)通信。文件内含测试文档,已在Modelsim6.5上测试通过,可在FPGA上直接调用。-A SPI Master code edited by VHDL language,the SPI modul use 0 MODE(i.e CPOL=0,CPHA=0)to communicate with the SPI Slave.and there is a testbench in the file folder,which has been tested in Modelsim6.5,you can use it in FPGA directly.
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Size: 3072 |
Author: 骏 |
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Description: VMM1.2的SPI示例代码,介绍各个验证组件的功能和用法。Verilog编写,使用VCS仿真-The example SPI testbench code of the VMM1.2
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Size: 1856512 |
Author: Tianlq |
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Description: SPI Master Core
HDL: VHDL 93
Compatibility: all FPGAs, CPLDs
parameterization:
- variable data width
- Phase/polarity configurable
- selectable buffer depth
- serial clock devision due to system clock
package usage:
IEEE.STD_LOGIC_1164
IEEE.NUMERIC_STD
work.general_signal_processing_pkg (included)
Testbench for simulation included.
Core Tested on Lattice XP2 CPLD Brevia development kit and FPGAs Xilinx Spartan-3E and Altera Cyclone-4E (industrial application)
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Size: 17408 |
Author: AgentNguyex |
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Description: THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
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Size: 780288 |
Author: LEE |
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Description: SPI master VHDL realisation
Also contains TestBench
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Size: 2048 |
Author: Stan |
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Description: It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
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Size: 2048 |
Author: eren |
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Description: spi slave的verilog程序,有测试平台testbench程序,实现fpga作为salve的功能(spi slave verilog program)
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Size: 5120 |
Author: CARL_2018 |
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Description: SPI FLASH官方仿真模型方便modelsim testbench调试仿真(Official simulation model facilitates debugging and simulation)
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Size: 1673216 |
Author: chengruiqi |
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