Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - system verilog for verification

Search list

[Other] VMMforSystemVerilog

Description: VMM for SystemVerilog中文版 Synopsys推崇SystemVerilog的设计和验证语言 这是一本很好的电子书-VMM for SystemVerilog Chinese version of Synopsys highly SystemVerilog design and verification language This is a very good e-book
Platform: | Size: 435200 | Author: stevephen | Hits:

[Other] systemverilog

Description: systemverilog3.1a的中文版（chm）和英文版（pdf），IC设计和验证发展的大趋势，绝对物超所值，希望对IC设计者有所帮助-systemverilog3.1a the Chinese version (chm) and English (pdf), IC design and verification development trends, the absolute value for money, and they hope to help IC designers
Platform: | Size: 4560896 | Author: Vallen | Hits:

[Other] vmm_sv

Description: vmm for SystemVerilog，是硬件开发很好的验证方法学资料-vmm for SystemVerilog, it is a very good hardware development data verification
Platform: | Size: 3333120 | Author: kljlj | Hits:

[VHDL-FPGA-Verilog] systemverilog

Description: system verilog 是国际流行的设计和验证语言，根据语言的特点分为两部分:for设计和for验证。另外一种书是介绍如何应用system verilog, 如果你要用syntem verilog, 推荐先读一下。-system verilog is popular hardware design and verification language. The languange compose of two part: systemverilog for desin , system verilog for test . in the rar package , a book introducing system verilog is recommanded.
Platform: | Size: 6114304 | Author: jhv | Hits:

[Other] ovm-2.0.2

Description: OVM(Open Verification Methdology) for system verilog or systemC
Platform: | Size: 3027968 | Author: ASURA | Hits:

[VHDL-FPGA-Verilog] SystemVerilogforDesign2ndEdition

Description: System Verilog for design verification
Platform: | Size: 2354176 | Author: JK | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现 第12章 XILINX硬核模块的VERILOG HDL调用 第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] SystemVerilogforVerification2ndEd

Description: ebook for System Verilog for Verification second edition
Platform: | Size: 1946624 | Author: sina_elec | Hits:

[VHDL-FPGA-Verilog] Writing-Testbenches-using-System-Verilog.tar

Description: Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I s and O s to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.
Platform: | Size: 2775040 | Author: ynona | Hits:

[VHDL-FPGA-Verilog] SystemVerilog-for-Verification--2nd-Ed

Description: This a system verilog book.-This is a system verilog book.
Platform: | Size: 1946624 | Author: sikki | Hits:

[VHDL-FPGA-Verilog] sv-for-Verification-2nd

Description: System Verilog for Verification, 2nd Edition.非常经典的资料，供IC开发的人员作自测平台或者验证的人员使用-System Verilog for Verification, 2nd Edition. Very classic information for IC self-test platform for the development of personnel for use by or verification
Platform: | Size: 1982464 | Author: linhaidu | Hits:

[VHDL-FPGA-Verilog] Verilog-Digital-System-Design

Description: Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
Platform: | Size: 8890368 | Author: 鲁智深 | Hits:

[VHDL-FPGA-Verilog] switch_system_verilog

Description: It is verification environment made in system verilog for verification of switch
Platform: | Size: 10240 | Author: urvish | Hits:

[VHDL-FPGA-Verilog] system-verilog-books

Description: SYSTEM VERILOG FOR VERIFICATION BOOK
Platform: | Size: 16860160 | Author: subeg | Hits:

[VHDL-FPGA-Verilog] SystemVerilog-for-Verification

Description: 经典的system verilog 教程。英文原版。-system verilog english version ， very useful
Platform: | Size: 1982464 | Author: james | Hits:

[VHDL-FPGA-Verilog] System-Verilog-for-Verification

Description: System Verilog for Verification，第二版，Chris Spear著的，对System Verilog的仿真与验证描述的很详细-System Verilog for Verification，Second Edition
Platform: | Size: 1987584 | Author: 陶龙远 | Hits:

[VHDL-FPGA-Verilog] System_Verilog_for_Verification

Description: System Verilog for Verification
Platform: | Size: 2000896 | Author: Forest | Hits:

[Other] SystemVerilog-for-Verification

Description: system verilog verifcation
Platform: | Size: 1169408 | Author: nakata free | Hits:

[Linux-Unix] SystemVerilog-for-Verification

Description: system Verilog for verification
Platform: | Size: 1185792 | Author: 彭久涛 | Hits:

[VHDL-FPGA-Verilog] Writing Testbenches using System Verilog

Description: Material to learn how to use system verilog and how to write testbenches for verification.
Platform: | Size: 2763776 | Author: DRAGON2018 | Hits:
« 12 »

CodeBus www.codebus.net