Description: In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx
Alliance tools and Synplicity Synplify.-In this paper, a new method is introduced to implement chaotic generators based on the Henon map and Lorenz chaotic generators given by the state equations using the Field Programmable Gate Array (FPGA). The aim of this method is to increase the frequency of the chaotic generators. The new method is based on the MATLAB® Software, Xilinx System Generator, Xilinx
Alliance tools and Synplicity Synplify. Platform: |
Size: 253952 |
Author:gsbnd |
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Description: 使用MATLAB为System Generator for DSP创建IP-The use of MATLAB for System Generator for DSP to create IP Platform: |
Size: 39936 |
Author:lxd |
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Description: Xilinx system generator的上手指南，system generator用于在matlab中使用simulink设计硬件，很方便-guide of system generater by Xilinx Platform: |
Size: 1685504 |
Author:王静 |
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Description: 基于软件无线电的SFF平台，采用Xilinx System Generator实现的数字上变频器-SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter Platform: |
Size: 53248 |
Author:刘荣毅 |
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Description: Introduction
Setting up the System Generator
Tool
A Quick Tour of the System
Generator
System Generator Basic Tutorial-Introduction Setting up the System Generator Tool A Quick Tour of the System Generator System Generator Basic Tutorial Platform: |
Size: 575488 |
Author:bobor |
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Description: Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro Platform: |
Size: 10615808 |
Author:rakesh |
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Description: 介绍了在xilinx环境中利用system generator设计数字上变频DUC/数字下变频DDC的流程，对于初学者很有帮助-introduced the design of DUC/DDC using system generator under xilinx, it s quite helpful to fresh Platform: |
Size: 2526208 |
Author:谢宾 |
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Description: This a Simulink model that demonstrates an algorithm that applies wireless security on physical layer. The demonstration is based on 802.11a (simplified) and receiver is implemented on Xilinx Virtex 4 FPGA.
The RAR file inlcudes 2 files:
1. Simulink model
2. initialization file.
Software requirements:
1. Matlab, r2007a or later
2. Simulink with DSP and Comm blocksets
3. Xilinx ISE with System Generator for DSP 9.2i or later. Platform: |
Size: 160768 |
Author:徐滨 |
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