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[Other resourceVHDL-ysw

Description: 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能,第二个CNT60实现分钟的计时功能,CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能,当秒种计时模块计时到59时向分种计时模块进位,同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位,到1小时59分59秒时,全部清零。同时,开关K1可以在两小时内暂停秒钟计时模块,分钟计时模块和小时计时模块。各模块的VHDL语言描述如下:-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows :
Platform: | Size: 2716 | Author: 杨仕伟 | Hits:

[VHDL-FPGA-Verilogpinlvji 频率计VHDL编程

Description: 频率计VHDL编程。设计一个4位数字显示的十进制频率计,其测量范围为1MHz,测量值通过4个数码管显示以8421BCD码形式输出,可通过开关实现量程控制,量程分10kHz、100kHz、1MHz三档(最大读数分别为9.999kHz、99.99kHz、999.9kHz); 当输入信号的频率大于相应量程时,有溢出显示。 -Cymometer VHDL programming. Design of a 4-digit decimal display frequency, the measurement range of 1MHz, the measured value through the four LED 8421BCD code shows the form of output can be controlled through the switch range, range at 10kHz, 100kHz, 1MHz Three (maximum reading were 9.999kHz, 99.99kHz, 999.9kHz) when the input signal is greater than the corresponding frequency range, it shows overflow.
Platform: | Size: 90168 | Author: testsb | Hits:

[SCM急救车与交通灯

Description: 急救车与交通灯)(1)南北与东西方向,每个方面由红黄绿三个灯控制(2)南北向: 红(30秒),黄(5秒),绿(25秒)   东西向: 红(35秒),黄(5秒),绿(25秒)   上述基本参数可以根据实际情况自行调整,灯的变化规律与实际路口规律相同,绿灯在最后5秒钟时,黄灯亮,然后红灯亮,不允许两个方面同时亮绿灯。(3)绿灯的时间显示在数码管上进行显示。(4)可以通过一个开关控制,当开关信号为0时,整个交通灯全灭提高要求:(1)设计一个紧急控制开关信号,当紧急开关信号为1时,两个方向的灯全为红灯。紧急开关撤消后,按照开关按下之前的状态继续运行(其参数要保存)。(2)设计一个夜间行车开关,当开关按下后,两个方向都只有黄灯闪烁,其它灯熄灭。(3)设计两个方向的亮时时间可调。-emergency vehicles and traffic lights) (1) North and South and east-west direction, each with three yellow-green from red lights control (2) to the north and south : red (30 seconds), yellow (5 seconds), Green (25 seconds) to things : red (35 seconds), yellow (5 seconds) Green (25 seconds) above basic parameters can be adjusted to the actual situation, the light changes with the actual law of the same intersection, the green light in the final five seconds, the yellow light is on, and then a red light, bright, not two fronts simultaneously bright green. (3) the green light at the time displayed on the digital display control. (4) can be controlled by a switch, when the switch signal to 0, the whole prospect of traffic lights to improve requirements : (1) Design an emergency control switch
Platform: | Size: 1024 | Author: dd | Hits:

[SCMAD_ASM_AD0832shuzidianyabiaoLED

Description: 数字电压表 AD芯片: 采用8位串行A/D转换器ADC0832。 ● 8位分辨率,逐次逼近型,基准电压为 5V ● 5V单电源供电 ● 输入模拟信号电压范围为 0~5V ● 有两个可供选择的模拟输入通道 显示: 使用三个数码管。 显示范围: 0.00 - 5.10 (单位:V) 连接方式: AD_CLK → P1.0 AD_DAT → P1.1 AD_CS → P3.4 模拟输入 → CH0 (AD_DAT = DO + DI) ADC0832输出最大转换值=FFH (255) 设定最大测量值=5.1V 255X=5.1 X=0.02 即先乘2再除以100 (小数点放在第三位数码管)- Digital voltmeter AD chip: Uses 8 serial A/D switch ADC0832.* 8 resolution, gradually approaching, the datum voltage is 5V* the 5V single power source power supply* input simulated signal voltage scope is 0 ~ 5V* has two to be possible to supply the choice the analog input channel Demonstrated: Uses three digital tubes. Demonstrates the scope: 0.00- 5.10 (unit: V) Connection way: AD_CLK-> P1.0 AD_DAT-> P1.1 AD_CS-> P3.4 analog input-> CH0 (AD_DAT = DO DI) ADC0832 output biggest transformation value = FFH (255) establishes greatest observed value = 5.1V 255X=5.1 X=0.02 namely first to ride 2 to eliminate again by 100 (decimal point puts on third digital tube)
Platform: | Size: 7168 | Author: lmhit | Hits:

[VHDL-FPGA-VerilogVHDL_Development_Board_Sources

Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock.
Platform: | Size: 4642816 | Author: Jawen | Hits:

[VHDL-FPGA-VerilogVHDL-ysw

Description:
Platform: | Size: 2048 | Author: 杨仕伟 | Hits:

[Software EngineeringDigitalssStopwatch

Description: 本秒表计时器用于体育竞赛及各种要求有较精确时的各领域。此计时器是用一块专用的芯片,用VHDL语言描述的。它除开关、时钟和显示功能以外,它还包括1/100s计时器所有的控制和定时功能,其体积小,携带方便。-the stopwatch timer for the various sports competitions and requires more accurate at the various fields. This timer is a dedicated chip, using the VHDL description. In addition to its switch, the clock and display functions, but also include 1/100 seconds timer control and all the regular functions, its small size and easy to carry.
Platform: | Size: 7168 | Author: 段苛苛 | Hits:

[VHDL-FPGA-Verilogvhdl_i2c

Description: 7. IIC 接口EEPROM 存取实验 按动开发板键盘某个键CPLD 将拨码开关的数据写入EEPROM 的某个地址,按动另 外一个键,将刚写入的数据读回CPLD,并在数码管上显示。帮助读者掌握I2C 的总线协 议和EEPROM 的读写方法。-7. IIC EEPROM Access Interface Development Board experimental pressed a button keyboard CPLD code will go into the data switch E EPROM a certain address, pressed another button, just write the data back to reading CPLD, and the digital pipe show. To help readers master the I2C bus protocol and EEPROM read and write methods.
Platform: | Size: 419840 | Author: 赵海东 | Hits:

[VHDL-FPGA-Verilog6FloorLift

Description: 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关,电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式(上升或者下降)指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层,经过1秒电梯门打开,开门4秒后,电梯门关闭(开门指示灯灭),电梯继续运行,直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号,并按照电梯运行规则按顺序响应,每个请求信号保留至有电梯响应后消除。 6、初始状态为一层开门,第一层不用向下开关,最高层不用向上开关。 7、电梯运行规则:当电梯上升时,只响应比电梯所在位置高的上楼请求信号,由下而上逐个执行,直到最后一个上楼请求执行完毕;如果高层有下楼请求,则直接升到下楼请求的最高楼层,然后进入下降模式。当电梯处于下降模式时与上升正好相反。 -design of a six-story elevator controller. Elevator Controller in accordance with the requirements of passengers automatically, the device. 1, installed on each floor elevator entrance next request switches, elevator begins to reach the level of customer stops request switch. 2, the location of elevator and escalator installations instructions operation mode (up or down) device instructions. 3, Elevator per second floor landing. 4, the lift reached a request stops floors seconds after an elevator doors open door four seconds later, elevator doors closed (to open the door to eliminate light), the continued operation of the lift, End until the implementation of the final request for a signal to stay in the current layer. 5, the lift will lift internal and external memory signal to all reques
Platform: | Size: 2048 | Author: zheng | Hits:

[OtherDAC0832

Description: vhdl代码多路开关,小系统使用,非常方便-VHDL code multi-channel switch, a small system, a very convenient
Platform: | Size: 1024 | Author: gcy | Hits:

[Embeded-SCM DevelopWatchdogTimer

Description: 用quartusII编写的,基于vhdl语言的按键加法器,从0到11,也可通过拨码开关控制,从11到0,加入了键盘防手抖。-QuartusII prepared to use, based on the VHDL language button adder, from 0-11, also available via dial code switch control, from 11-0, joined the anti-tremor keyboard.
Platform: | Size: 2048 | Author: yl | Hits:

[Otherswitch

Description: 四个拨码开关,拨上去对应的前四个LED灯亮,体现了pld io功能的灵活。请把拨码开关右上方的跳线帽跳上,同时拔掉ADC0804的跳线帽。-Four DIP switches, dial up the corresponding first four LED lights, reflect the function of flexible pld io. Please dial code switch at the top right of the jumper cap jumped, and pulled out the jumper cap ADC0804.
Platform: | Size: 64512 | Author: liupeinan | Hits:

[VHDL-FPGA-VerilogSF_table_interface

Description: switch fabric部分代码: fabric和table management 的数据交换. Mac address 从afifo输入, 查询的结果:output port number 存于pfifo中-switch fabric part of the code: fabric and table management data exchange. Mac address from afifo input, the results of inquiries: output port number stored in Medium pfifo
Platform: | Size: 2048 | Author: 无影 | Hits:

[SCMS3_SW

Description: 这个程序是用来测试拨码开关与按键开关的, 当按下按键开关时,相应的led会点亮, 同理打开拨码开关相应的led也会点亮-This procedure is used to test switch DIP switch and button, when pressing the button switch, the corresponding led will light up, open the same token the corresponding DIP switch led will be lit
Platform: | Size: 188416 | Author: 刘飞 | Hits:

[ActiveX/DCOM/ATLCross_Bar_Switch_Codes

Description: Cross Bar Codes for Cross Bar switch Communication
Platform: | Size: 10240 | Author: Vas | Hits:

[OtherHV_SWITCH_VHDL

Description: 此VHDL程序以HV的示例进行8路输入与8路输出的选择设置,以此演示最基本的矩阵切换功能。压缩包中含有一份说明文件,详细说明应用情况。-The VHDL program to HV examples 8 to 8-way input and output options settings, this demonstrates the most basic function of a matrix switch. Compressed packet contains a document with the detailed description of the application.
Platform: | Size: 7168 | Author: Jacob | Hits:

[VHDL-FPGA-VerilogVHDL(LOCK)

Description: 数字密码锁的设计与实现 一.实验目的 1. 学习VHDL的综合设计应用 2. 学习数字密码锁的设计 二.实验内容 设计一个数字密码锁,对其编译,仿真,下载。 数字密码锁具体要求如下: 1.系统具有预置的初始密码“00000001”。 2.输入密码与预存密码相同时,开锁成功,显示绿灯,否则开锁失败,显示红灯。 3.具有修改密码功能。修改密码时,先开锁,开锁成功才可以修改。 4.系统同时具有关锁功能。关锁后,显示红灯。 5.密码由拔码开关表示,开锁由按键表示。 6具有一个复位按键。按键后,回到初始状态。 -VHDL Digital Design and Implementation of lock 1. Purpose of the experiment 1. VHDL Integrated Design and Application of Learning 2. Learning digital code lock design 2. Experimental content Design a digital lock on their compilation, simulation, download. Digital code lock specific requirements are as follows: 1. System has preset the initial password "00000001." 2. Enter the same password with the stored password, unlock successful, a green light, or unlock failed to show a red light. 3. With the change password function. Modify password, the first lock, unlock success can modify. 4. The system also has off lock. Shut up after the red light. 5. The password code from the pull switch that unlock the keys, said. 6 has a reset button. Button, the return to initial state.
Platform: | Size: 18432 | Author: 爱好 | Hits:

[VHDL-FPGA-VerilogVHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示(设为A数)。 3梯运行的楼层数可自动显示(设为B数)。 4A>B时,系统能输出使三相电机正转的时序信号,使电梯上升; 当A<B时,系统能输出使三相电机反转的时序信号,使电梯下降; 当A=B时,系统能输出使三相电机停机的信号,使电梯停止运行并开门; 5是上升还是下降各层电梯门外应有指示,各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。 注:此为word文档,但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-VerilogVHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来,这里采用动态分时总线切换电路对数码管进行扫描,对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

[VHDL-FPGA-Verilogvhdl-code-for--A-HIGH-SPEED-SYMMETRIC-CROSSBAR-SW

Description: vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH-vhdl code for A HIGH SPEED SYMMETRIC CROSSBAR SWITCH
Platform: | Size: 13312 | Author: a.arezoo60 | Hits:
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