Search - stack in verilog

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[Other resource] verilogfifo DL : 0: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Date : 2008-10-13 Size : 1.38kb User : zzm
[Other resource] DDS_Power DL : 0: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Date : 2008-10-13 Size : 15.85kb User : 田世坤
[VHDL-FPGA-Verilog] verilogfifo DL : 0: verilog HDL实现先进先出栈，不含测试文件-verilog HDL achieve first-in first-out stack, non-test document
Date : 2025-07-12 Size : 1kb User : zzm
[VHDL-FPGA-Verilog] DDS_Power DL : 0: FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。-FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.
Date : 2025-07-12 Size : 16kb User : 田世坤
[Other] Memory DL : 0: Example of a FIFO code in verilog language, to control a bus. With a memory stack and a testbench.
Date : 2025-07-12 Size : 827kb User : Lokous
[Other] Stack DL : 0: Implementation of 8 level deep stack in PIC1684fA using Verilog in structural mode
Date : 2025-07-12 Size : 17kb User : ayood
[VHDL-FPGA-Verilog] sv DL : 0: stack and events in system verilog
Date : 2025-07-12 Size : 1kb User : Kiran
[VHDL-FPGA-Verilog] flow_proc DL : 0: 流水线结构是在逻辑很复杂的情况下使用，通过分栈，把一个复杂的逻辑分成若干个比较简单的块实现，减少信号的逻辑级，提高频率。最形象的实例就是位宽较大的加法器。此程序就是verilog的实现 -In the pipeline structure is complex logic case, through the sub-stack, the complex logic into a plurality of blocks of a relatively simple implementation, the logic level signal decrease, increase frequency. The most vivid example is the bit width larger adder. This program is the realization of verilog
Date : 2025-07-12 Size : 224kb User : jodyql
[VHDL-FPGA-Verilog] stack DL : 0: 根据堆栈逻辑结构，使用Verilog编写的一个堆栈，并通过仿真实现了功能-fist in last out
Date : 2025-07-12 Size : 4.3mb User : 舒占军
[VHDL-FPGA-Verilog] udp_send1 DL : 0: 基于FPGA的UDP硬件协议栈，全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。支持外部phy的配置，支持GMII和RGMII模式。以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Date : 2025-07-12 Size : 52kb User : qiubin