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[VHDL-FPGA-Verilog] divider

Description: 此代码用于实现基2的SRT除法器设计，可以实现400MHz以上的32位定点无符号数除法器（除数、被除数和余数均由16位整数和16位小数组成，商由32位整数和16位小数构成,包括源代码和测试文件，可以直接仿真。-This code used to realize the base 2 SRT divider design, you can realize more than 400MHz unsigned 32-bit fixed-point divider number (divisor, dividend and the remainder by the 16-bit integer and 16 fractional composition operators from 32-bit integer and 16 decimal places, including the source code and test files, you can direct simulation.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

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[VHDL-FPGA-Verilog] divider

[VHDL-FPGA-Verilog] 10.1.1.104.9024

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