Search - spi master vh

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] SPI_collect

Description: 有关SPI的vhdl实现。包括SPI官方协议，几篇开发时用到的论文，附加了中文注释的SPI IPcore，还有一个经过简化的master mode的SPI实现的vhdl代码-Related to the VHDL SPI realize. Including SPI official agreement, when used to develop several theses, Chinese notes attached SPI IPcore, there is a simplified master mode the SPI realize the VHDL code
Platform: | Size: 1334272 | Author: danielmu | Hits:

[VHDL-FPGA-Verilog] spi_master_control

Description: VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
Platform: | Size: 670720 | Author: lonely_vv | Hits:

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[VHDL-FPGA-Verilog] spi

[VHDL-FPGA-Verilog] spi_op_core

[VHDL-FPGA-Verilog] SPI_collect

[VHDL-FPGA-Verilog] spi_master_control

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