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[Other] SPI_Verilog

Description: SPI的verilog 核
Platform: | Size: 81010 | Author: tiangang1975@gmail.com | Hits:

[VHDL-FPGA-Verilog] vspi

Description: verilog VSIP core,用verilog语言编写，希望对各位朋友有所帮助！-verilog VSIP core, using Verilog language, and they hope to help all our friends!
Platform: | Size: 13312 | Author: liuzinan | Hits:

[VHDL-FPGA-Verilog] spi_op_core

Description: 串行数据SPI master的开源控制器，verilog，内附说明-SPI master serial data open-source controller, verilog, containing a description
Platform: | Size: 81920 | Author: 王天 | Hits:

[VHDL-FPGA-Verilog] xilinx_iic_spi

Description: xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
Platform: | Size: 1765376 | Author: 杨子树 | Hits:

[VHDL-FPGA-Verilog] SPI_verilog_vhdl

Description: SPI串口的内核实现（分别使用verilog和vhdl语言描述的）-The core of the realization of SPI serial port (using Verilog and VHDL language description of the)
Platform: | Size: 13312 | Author: 徐剑 | Hits:

[Embeded-SCM Develop] spi_op_core

Description: SPI协议的Verilog编程，包括时钟的产生模块，控制模块等-Verilog programming SPI protocol, including the selection of the clock module, control module, etc.
Platform: | Size: 82944 | Author: zhangyi | Hits:

[VHDL-FPGA-Verilog] 43680540SPI_Core

Description: Verilog for SPI Core source code
Platform: | Size: 14336 | Author: J.M Yang | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI IP CORE Verilog quartus-SPI IP CORE Verilog quartusii
Platform: | Size: 1487872 | Author: thegreeneyes | Hits:

[VHDL-FPGA-Verilog] CoreSPI_21_eval

Description: SPI IP核源码，包括Verilog和VHDL两种语言源码-SPI IP core source code, including the two languages ​ ​ Verilog and VHDL source code
Platform: | Size: 628736 | Author: 任林枫 | Hits:

[VHDL-FPGA-Verilog] verilog-SPI-core

Description: 用VerilogHDL写的spi 核的例子-A simple example of SPI core using Verilog HDL
Platform: | Size: 49152 | Author: guorui | Hits:

[VHDL-FPGA-Verilog] SPI

Description: Verilog编写的SPI程序，含英文原文档说明，很全的-The OpenCores simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, synchronous communication protocol that requires a minimum of 3 wires. Enhancements to the original interface include a wider supported operating frequency range, 4 entries deep read and write FIFOs, and programmable transfer count dependent interrupt generation. The high compatibility with the M68HC11 SPI port ensures that existing software can use this core without major modifications. New software can use existing examples as a starting point. The core features an 8 bit wishbone interface.
Platform: | Size: 49152 | Author: 邓楠 | Hits:

[Other] SPI_Core_2

Description: 用Verilog HDL 语言编写的，可在FPGA上实现的SPI总线主端 收发读写模块 -SPI Master Read-Write controller core which was Writted by Verilog HDL based on fpga
Platform: | Size: 2048 | Author: FEIFEI | Hits:

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