Description: The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file, PICCPU.VHD and common questions are answered
in the file SYNTHPIC.TXT
Files:
README.TXT This file..
SYNTHPIC.TXT Questions and Answers
PICCPU.VHD Main processor VHDL file
PICALU.VHD ALU for the PICCPU
PICREGS.VHD Data memory
PICROM.VHD Program memory (created by HEX2VHDL utility)
PICTEST.VHD Simple test bench I used to do testing (optional)
PICTEST.CMD My Viewlogic ViewSim command file (again, optional)
TEST1.ASM First program I assembled and ran on it.
TEST2.ASM Another test program..
TEST3.ASM Yet another..
TEST4.ASM Yet another..
TEST5.ASM Yet another..
TEST6.ASM Yet another..
HEX2VHDL.CPP Utility for converting -The Synthetic PICVerion 1.1This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.It is not, and is not intended as, a high fidelity circuit simulation.This package includes the following files. Note that the license agreementis stated in the main VHDL file , PICCPU.VHD and common questions are answeredin the file SYNTHPIC.TXTFiles: README.TXT This file .. SYNTHPIC.TXT Questions and AnswersPICCPU.VHD Main processor VHDL filePICALU.VHD ALU for the PICCPUPICREGS.VHD Data memoryPICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it.TEST2.ASM Another test program. . TEST3.ASM Yet another .. TEST4.ASM Yet another .. TEST5.ASM Yet another .. TEST6.ASM Yet another .. HEX2VHDL.CPP Utility for converting Platform: |
Size: 48128 |
Author:likui |
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Description: Prawn is a simple eight-bit microprocessor based on the sample processor described in Chapter 9 of "VHDL : Analysis and Modeling of Digital Systems"by Z. Navabi, McGraw-Hill,Inc. 1993. We have added some features such as interrupt, stack and some conditions for conditional branch to the example in the book.
-Prawn is a simple eight-bit microprocessor based on the sample processor described in Chapter 9 of "VHDL : Analysis and Modeling of Digital Systems"by Z. Navabi, McGraw-Hill,Inc. 1993. We have added some features such as interrupt, stack and some conditions for conditional branch to the example in the book.
Platform: |
Size: 698368 |
Author:ying |
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Description: 简化的单时钟循环VHDL处理器.可以运行一些简单的mips指令，例如add, sub, and, or, slt, beq and j. -A simplified single cycle processor in VHDL. This processor can continuously execute some simple MIPS instructions which are lw, sw, add, sub, and, or, slt, beq and j. Platform: |
Size: 191488 |
Author:糖醋鱼 |
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Description: The SAYEH (Simple Architecture, Yet Enough Hardware) is a processor architecture that has been developed by Navabi in [1] for experimental and teaching purposes. As the name implies it is a “simple” architecture but contains sufficient hardware to make it a challenge. In this and the following workshops we will be developing this processor architecture to practice our skills in developing VHDL code which will be useful in later laboratories when we will be building more complex structures. Unfortunately the SAYEH code provided by Navabi is written in Verilog, we will be translating it to VHDL. Platform: |
Size: 41984 |
Author:jiang nan |
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