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[Compress-Decompress algrithmssha1sourcecode

Description: 本代码是SHA1用C语言实现的源代码,SHA1与MD5是目前最为常用的HASH算法,可用于认证及签名等-This code is SHA1 with C language source code, SHA1 and MD5 is currently the most commonly used HASH algorithm, can be used for authentication and signatures
Platform: | Size: 53248 | Author: cl | Hits:

[Crack Hacksha

Description: 内带3个sha1的C源码。经验证都可用。在我们项目中,已经用于验证SHA1的verilog-With three within the C source code sha1. Experience certificate are available. In our project, has been used to validate SHA1 of verilog
Platform: | Size: 14336 | Author: 左宏权 | Hits:

[VHDL-FPGA-VerilogSHA1

Description: SHA1 implementation on FPGA VHDL code
Platform: | Size: 3072 | Author: osman | Hits:

[Software Engineeringsha1_v01

Description: sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equation of core is frequency in MHz * (512bits/block) / (81 rounds/block). The cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7 FPGA which results in 700 Mbps processing rate. Note: This calculation ignores the effect of a partially full last block Finally, Padding, HMAC, and bus interface functionality is not provided. These will vary with the particular system design. The core size is about 800 Xilinx Virtex II FPGA Family Slices. I welcome feedback on any aspects of this design.-sha1_testbench.v -- Testbench with vectors NIST FIPS 180-2 sha1_exec.v -- Top level sha1 module sha1_round.v -- primitive sha1 round dffhr.v -- generic parameterizable D-flip flop library Performance Analysis Performance equation of core is frequency in MHz * (512bits/block) / (81 rounds/block). The cycle time is approximately 9.0ns for Xilinx xc2vp7-ff896-7 FPGA which results in 700 Mbps processing rate. Note: This calculation ignores the effect of a partially full last block Finally, Padding, HMAC, and bus interface functionality is not provided. These will vary with the particular system design. The core size is about 800 Xilinx Virtex II FPGA Family Slices. I welcome feedback on any aspects of this design.
Platform: | Size: 6144 | Author: sam | Hits:

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