Search - sequence detector

[VHDL-FPGA-Verilog] xljcq

Description: 用vhdl语言实现序列检测器的设计这是学习VHDL语言的经典例子-Using VHDL language sequence detector design VHDL language learning this is a classic example of
Platform: | Size: 3072 | Author: 郭海东 | Hits:

Description: 序列发生器,产生一个8位序列号,序列码可自定义修改,还有一个序列检测器 -Sequence generator, producing an 8-bit serial number, serial code can be customized to amend, there is a sequence detector
Platform: | Size: 784384 | Author: 郭明 | Hits:

[VHDL-FPGA-Verilog] detecter

Description: 这是序列检测器。串行序列产生是指根据时钟和相应的控制信号，产生稳定的单bit输出信号；监测器指根据相应时钟输入的电平序列，监测该序列中是否存在预设的序列，无论从第几个输入开始，只要存在，总能监测到。监测到予以标示。-This is the sequence detector. Have a serial sequence is defined as the clock and the corresponding control signal, producing a stable single-bit output signal monitor means the corresponding clock input sequence level, monitoring the sequence of the existence of the default sequence, whether from the first few enter a start, as long as there is, always monitored. Monitoring to be marked.
Platform: | Size: 101376 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] chk

Description: 本程序实现了一个序列检测器。当一串待检测的串行数据进入检测器后，若此数在每一位的连续检测中都与预置的密码数相同，则输出“A”,否则仍然输出“B”。-This procedure implements a sequence detector. When a string of serial data to be tested after entering the detector, if the number in each successive detection with the same number of preset password, then output A , otherwise the output is still B .
Platform: | Size: 1024 | Author: liushenshen | Hits:

[VHDL-FPGA-Verilog] detect

Description: 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。-A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Platform: | Size: 1024 | Author: chengpan | Hits:

[VHDL-FPGA-Verilog] sequence_inspector

Description: 序列检测器可用于检测一组或多组二进制码组成的脉冲序列信号，这在数字通信领域中有广泛的应用。当序列检测器连续收到一组二进制码后，如果这组码与检测器中预先设置的码相同，则输出1，否则输出0。由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到连续的检测中收到每一位都与预置数的对应码相同。在检测过程中，任何一位不相等都将回到初始状态重新开始检测。并附有测试程序-Sequence detector can be used to detect one or a binary code consisting of pulse sequence signal, which in the field of digital communications in a wide range of applications. When the sequence detector row received a group of binary code, if this group of codes and detectors in the same pre-set code, then output 1, otherwise output 0. As a result of this test lies in the receipt of the correct code must be continuous, which requires detector must be remembered that the previous code and correct the correct sequence, until the continuous detection and received every preset number of correspond to the same code. In the detection process, any one of unequal status will be returned to the initial detection of a fresh start. With test procedures
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilog] seg_test

Description: 基于VHDL的序列检测器设计-VHDL-based sequence detector design
Platform: | Size: 156672 | Author: peter | Hits:

[Other] code

Description: 使用状态机设计一个5位序列检测器。从一串二进制码中检测出一个已预置的5位二进制码-The use of state machines to design a sequence detector 5. From a string of binary code to detect a preset binary code of 5
Platform: | Size: 48128 | Author: evelyn | Hits:

[VHDL-FPGA-Verilog] 2

Description: 序列检测器VHDL语言设计和仿真和校验模块的程序和仿真结果 -Sequence detector design and simulation of VHDL language and the validation process modules and simulation results
Platform: | Size: 38912 | Author: 林露吟 | Hits:

[ELanguage] EP1C3_81_SCHK

Description: 序列检测器设计这里面是一个完整的工程可以直接适用-Sequence detector design there is a complete project can be applied directly
Platform: | Size: 7168 | Author: 小欧 | Hits:

[VHDL-FPGA-Verilog] Sequence-detector-design

Description: 序列检测器设计的思路大多都是用FSM来实现的,此思路是通过移位寄存器来实现序列检测-Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
Platform: | Size: 30720 | Author: lsp | Hits:

[Windows Develop] Sequencedetector

Description: 序列检测器可用来检测一组或多组由二进制码组成的脉冲序列信号，这在数字通信领域有广泛的应用。当检测器连续收到一组串行二进制码后，若这组码与检测器中预制的码相同，输出为A，否则输出为B。序列检测I/O口的设计如下：设Din是串行数据输入端，clk是工作时钟，clr是复位信号，D是8位待检测预置数，QQ是检测结果输出端。-Sequence detector can be used to detect one or more sets consisting of binary code from the pulse sequence signal, which is a broad field of digital communication applications. When the detector continuously received after a group of serial binary code, if this group of pre-code and the code detector in the same output as A, otherwise the output B. Sequence detection I/O port design are as follows: Let Din is the serial data input, clk is work the clock, clr is a reset signal, D is the 8-bit preset number to be detected, QQ is the test results output.
Platform: | Size: 4096 | Author: yufang | Hits:

[Other] Sequencedetector

Description: Sequence detector design ideas are often used to achieve the FSM, the idea is to achieve through the shift register sequence detection
Platform: | Size: 31744 | Author: jimmy sia | Hits:

[VHDL-FPGA-Verilog] fsm

Description: Sequence detector "1100101101" using FSM(Finite State Machine) in VHDL.
Platform: | Size: 401408 | Author: Aaqib | Hits:

[VHDL-FPGA-Verilog] Sequence-detector

Description: VHDL环境下编写的序列检测器，当检测到设定序列时，硬件的提示灯会亮，也会发出警示音。-Sequence detector written in VHDL environment, when detected, set the sequence, the light will also alert tone hardware tips.
Platform: | Size: 115712 | Author: 孙佳婷 | Hits:

[VHDL-FPGA-Verilog] 10101-sequence-detector

Description: 课程设计之10101序列检测器的Verilog 实现-10101 sequence detector
Platform: | Size: 1024 | Author: 陈俊辉 | Hits:

[VHDL-FPGA-Verilog] The-state-machine-sequence-detector

Description: 状态机实现序列检测器。设计一个一个左移移位寄存器，用硬件设备上的两个拔码开关，预置一个8位二进制数作为待检测码，随着时钟逐步输入序列检测器，8个脉冲后检测器输出结果。-The state machine sequence detector. Design a left shift register, two on the hardware DIP switch and preset an 8-bit binary number as to be detected code, as the clock gradually enter the sequence detector, detector output results after eight pulses.
Platform: | Size: 1468416 | Author: clementkv | Hits:

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