Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - root verilog

Search list

[Other resource] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15 * 21 ^ 6 a X * X ^ a ^ 15 2 * X ^ a ^ 3 25 * X ^ a ^ 4 17 5 * X ^ a ^ 18 ^ 6 X * a * X 30 ^ 7 ^ a ^ 20 * X ^ a ^ 23 8 * X ^ a ^ 9 * 27 X 10 ^ a ^ 24 * 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14247 | Author: 孟轲敏 | Hits:

[VHDL-FPGA-Verilog] rs_decoder_31_19_6.tar

Description: Hard-decision decoding scheme Codeword length (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents 5 bit. Uses GF(2^5) with primitive polynomial p(x) = X^5 X^2 + 1 Generator polynomial, g(x) = a^15 a^21*X + a^6*X^2 + a^15*X^3 + a^25*X^4 + a^17*X^5 + a^18*X^6 + a^30*X^7 + a^20*X^8 + a^23*X^9 + a^27*X^10 + a^24*X^11 + X^12. Note: a = alpha, primitive element in GF(2^5) and a^i is root of g(x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizable RTL modelling. Consists of 5 main blocks: SC (Syndrome Computation), KES (Key Equation Solver), CSEE (Chien Search and Error Evaluator), Controller and FIFO Register. -Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) = x ^ x ^ 5 2 1 Ge nerator polynomial. g (x) = a ^ a ^ 15* 21 ^ 6 a X* X ^ a ^ 15 2* X ^ a ^ 3 25* X ^ a ^ 4 17 5* X ^ a ^ 18 ^ 6 X* a* X 30 ^ 7 ^ a ^ 20* X ^ a ^ 23 8* X ^ a ^ 9* 27 X 10 ^ a ^ 24* 11 ^ X ^ X 12. Note : a = alpha, primitive element in GF (2 ^ 5) and a ^ i is the root of g (x) for i = 19, 20, ..., 30. Uses Verilog description with synthesizab le RTL modeling. Consists of five main blocks : SC (Syndrome Computation), KES (Key Equation Solver). CSEE (Chien Search and Error Evaluator) Controller and FIFO Register.
Platform: | Size: 14336 | Author: 许茹芸 | Hits:

[VHDL-FPGA-Verilog] alu-div

Description: 用verilog HDL代码编写的快速除法器，比较有用
Platform: | Size: 15360 | Author: 徐芬 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: verilog 硬件平方根算法 采用与笔算平方根一样的算法-Verilog hardware and written calculation algorithm uses the square root of the square root of the same algorithm
Platform: | Size: 17408 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] HDL_design

Description:
Platform: | Size: 663552 | Author: Ning Zheng | Hits:

[VHDL-FPGA-Verilog] rrc_filter

Description: this is a verilog code for root raised cosine filter
Platform: | Size: 1024 | Author: vlsi | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: This zip file contains the verilog source code for square root calculation and its test bench
Platform: | Size: 2048 | Author: Jaganathan | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: 树式除法型开方器VERILOG实现,用于任意长度的无符号数的开方运算-Square root of the tree-type divider-type device to achieve VERILOG
Platform: | Size: 1024 | Author: 神气 | Hits:

[VHDL-FPGA-Verilog] square-root

Description: Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware description language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation available are introduced. This thesis include the design of square root machine which is based on the EasyFPGA030 ,as well as the details of the design process Verilog language use and achieve results.
Platform: | Size: 905216 | Author: stella | Hits:

[VHDL-FPGA-Verilog] sqrt_for_single_float_point

Description: 用verilog实现了基于中值定理求解单精度浮点开方的功能，希望对大家学习有所帮助-With verilog implemented based on the mean value theorem to solve single-precision floating point square root function, we want to study and help ... ...
Platform: | Size: 5120 | Author: 楚艳超 | Hits:

[VHDL-FPGA-Verilog] 470P2F07

Description: sqrt root using verilog
Platform: | Size: 129024 | Author: saluish | Hits:

[VHDL-FPGA-Verilog] in-ModelSim-and-Xilinx-lib

Description: 在ModelSim SE中配置Xilinx的库函数 在Modelsim的安装根目录下新建一个文件夹，用来放xilinx的各个库文件，故可以起名 xilinx_lib。类似于Xinlinx的安装文件：\..\\Xilinx\verilog\src中的各个库文件，在xilinx_lib文件 下新建各个文件夹，命名规则为：若src中的文件夹名为unisims，则在xilinx_lib文件夹下新建 为unisims_ver的文件夹，与此雷同，新建名为simprims_ver、XilinxCoreLib_ver、iSE_ver unisims_ver的各个文件夹。 -ModelSim SE configured in the library function in Modelsim Xilinx installation root directory create a new folder to put all the library files xilinx, it can be named xilinx_lib. Similar Xinlinx installation file: \ .. \ \ Xilinx \ verilog \ src in the various libraries in New xilinx_lib each folder under the file named rule: If the src folder named unisims, the file in the xilinx_lib new folder under the folder for the unisims_ver, and this similarity, the new name simprims_ver, XilinxCoreLib_ver, iSE_ver unisims_ver each folder.
Platform: | Size: 106496 | Author: 谢明 | Hits:

[VHDL-FPGA-Verilog] SQRT

Description: 用verilog代码编写的求整数平方根的FPGA工程。-Verilog code written request with the integer square root of the FPGA project.
Platform: | Size: 237568 | Author: 袁媛 | Hits:

[VHDL-FPGA-Verilog] CLK_DIV

Description: verilog HDL写的时钟通用计数分频程序，设置系统时钟，并根据目标时钟，设置分频系数即可得到目标时钟。已实际测试可用。-verilog HDL write clock common procedures for the count and divide, set the system clock, and the root According to the target clock, set the frequency division factor can get the target clock. Have been actual tested
Platform: | Size: 1024 | Author: fightsea | Hits:

[Other] Verilog

Description: 同济大学徐和根老师vhdl课程讲解的ppt-Vhdl course of Tongji University, Xu and root teacher to explain ppt
Platform: | Size: 35685376 | Author: 杨波 | Hits:

[VHDL-FPGA-Verilog] sqrt

Description: VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG description of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
Platform: | Size: 1024 | Author: Solomon | Hits:

[Windows Develop] cordic

Description: verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
Platform: | Size: 1024 | Author: 刘大远 | Hits:

[VHDL-FPGA-Verilog] QPSK_DSSS

Description: 该程序使用verilog语言，编写了QPSK-DSSS系统的发端，主要模块包括对同相分量和正交分量的扩频，通过根升余弦滤波器，以及与载波相乘等模块。-The program uses the verilog language, written QPSK-DSSS system, the originator, the main modules include in-phase and quadrature components of the spectrum, through the root raised cosine filter, as well as with carrier multiplication modules.
Platform: | Size: 6983680 | Author: 林源 | Hits:

[Other] adder

Description: 包含32位有无符号数的加减法，verilog语言描述，加法器分别采用行为级描述、行波进位、平方根进位三种描述方法，并有简单的testbench-32bits adder with addition and subtraction function. verilog HDL language . three kinds of implementations: adder behavioral description, ripple carry, the square root of the carry , with a simple testbench
Platform: | Size: 3072 | Author: D | Hits:

[VHDL-FPGA-Verilog] cube_root

Description: cube_root使用Verilog语言使用开立方根的算法-cube root
Platform: | Size: 3249152 | Author: Neddy | Hits:
« 12 »

CodeBus www.codebus.net