Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - random verilog

Search list

[Other resource] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback - shift-register
Platform: | Size: 1837 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] pseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[VHDL-FPGA-Verilog] 八位的伪随机数产生的verilog文件

Description: 八位的伪随机数产生的verilog文件linear-feedback-shift-register-eight pseudo-random number generator in Verilog document linear-feedback- shift-register
Platform: | Size: 2048 | Author: 陈正一 | Hits:

[Other] LDPC

Description: 用于LDPC编码译码的仿真实现。包括随机生成校验矩阵、由校验矩阵产生生成矩阵、编码、加随机噪声、译码等内容。原作者是老外，有部分中文注释。-LDPC coding for decoding Simulation. Check including random matrix generated by the calibration matrix generated generator matrix, coding, plus random noise, such as decoding. The original author is a foreigner, some Chinese Notes.
Platform: | Size: 58368 | Author: 别志松 | Hits:

[Algorithm] U-rand(0-100)

Description: 0-100伪随机数发生函数代码，希望程序能用得上，-0-100 pseudo-random number generating function codes, procedures can hope that none?
Platform: | Size: 1024 | Author: 陈波 | Hits:

[VHDL-FPGA-Verilog] 9.3_Pulse_Counter

Description: 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 　　9.3.1 脉冲计数器的工作原理 　　9.3.2 计数模块的设计与实现 　　9.3.3 parameter的使用方法 　　9.3.4 repeat循环语句的使用方法 　　9.3.5 系统函数$random的使用方法 　　9.3.6 脉冲计数器的Verilog-HDL描述 　　9.3.7 特定脉冲序列的发生 　　9.3.8 脉冲计数器的硬件实现 -based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[VHDL-FPGA-Verilog] ram

Description: RAM， Random-access memory，Verilog code-RAM, Random-access memory, Verilog code
Platform: | Size: 14336 | Author: leigh lee | Hits:

[Crack Hack] RC5

Description: 流密码算法,可用于文件加密和实时通信 ,设计者是著名的密码学家Rivest.该算法效率远高于一般分组密码,并且很适合用于随机数生成-Stream cipher algorithm, can be used for file encryption and real-time communication, the designer is well-known cryptographer Rivest. The algorithm efficiency is much higher than the general block cipher, and is suitable for random number generator
Platform: | Size: 2048 | Author: che wang | Hits:

[VHDL-FPGA-Verilog] rng

Description: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Platform: | Size: 94208 | Author: Alex | Hits:

[Other] rng_opencore

Description: opencore, random number generator, verilog
Platform: | Size: 3072 | Author: jason | Hits:

[VHDL-FPGA-Verilog] c21_pn_code_generator

Description: 精通verilog HDL语言编程源码之7——伪随机序列应用设计-Proficient in programming language source verilog HDL of 7- the application of pseudo-random sequence design
Platform: | Size: 1024 | Author: 李平 | Hits:

[Crack Hack] lfsr

Description: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] fcsr

Description: 伪随机序列产生器－代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilog] ffcsr

Description: 伪随机序列产生器－filtered 代进位反馈移位寄存器，verilog hdl 原代码。-Pseudo-random sequence generator-filtered on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 2048 | Author: 李辛 | Hits:

[Communication-Mobile] decoder

Description: 用verilog编写的bch译码器，包括测试文件，随机加载了比特流，进行了测试。-Prepared using Verilog BCH decoder, including test papers, random load the bit stream to carry out the test.
Platform: | Size: 357376 | Author: 牛顿 | Hits:

[VHDL-FPGA-Verilog] prbsforip

Description: 本文设计了一种简捷而又高效的伪随机序列产生方法，最后通过统计对比，说名这种方法产生的随机序列不仅周期长 还具有两好的随机特性-This paper designed a simple and efficient method for the selection of pseudo-random sequence, and finally through statistical comparison, saying that this method of random sequence generated by not only the long cycle and also has two well-randomness
Platform: | Size: 268288 | Author: 5656 | Hits:

[VHDL-FPGA-Verilog] Application_of_pseudo_random_sequence_verilog_desi

Description: 伪随机序列应用verilog设计.rar-Application of pseudo-random sequence verilog design.rar
Platform: | Size: 1024 | Author: 海天之洲 | Hits:

[VHDL-FPGA-Verilog] random

Description: Verilog使用$random()函數簡單範例-Verilog using the $ random () function of a simple example
Platform: | Size: 38912 | Author: 蕭鴻森 | Hits:

[Other] random frenquency division

Description: verilog任意分频代码，作为新思路参考(veriliog code used as reference to new idea)
Platform: | Size: 1024 | Author: qq956179683 | Hits:

[VHDL-FPGA-Verilog] random

Description: 用简单的线性反馈移位寄存器实现了伪随机数的生成…(The pseudo random number is generated by a simple linear feedback shift register)
Platform: | Size: 740352 | Author: fv_4 | Hits:
« 12 3 4 5 »

CodeBus www.codebus.net