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[Books] SignalTapII_HowTo

Description:
Platform: | Size: 1067008 | Author: | Hits:

[VHDL-FPGA-Verilog] qts_qii52003

Description: Quartus II Tcl Scripting说明文档，详细说明了在quartus中如何使用Tcl脚本进行快速开发。-Quartus II Tcl Scripting documentation detailing how to use the Quartus Tcl script for rapid development.
Platform: | Size: 240640 | Author: 杨开轶 | Hits:

[Other] TCLscript

Description: tcl脚本语言中文教程，可以看看，很不错的哦。-tcl scripting language English tutorial, you can see, very good, oh.
Platform: | Size: 618496 | Author: 相耀 | Hits:

[Embeded-SCM Develop] TCL_Training

Description:
Platform: | Size: 618496 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] NIOS_TFT

Description: 用Quartus II 8.0（32bit），NIOS编译环境下，用TFT做的一个数码相框，附加原理图和veri-log程序代码-Using Quartus II 8.0 (32bit), NIOS compiler environment, TFT do with a digital photo frame, attached schematic and program code veri-log
Platform: | Size: 14394368 | Author: 涂龙 | Hits:

[VHDL-FPGA-Verilog] mux4

Description: 四位乘法器的VHDL语言设计，并有原理图的描述-4 Multiplier VHDL language design, and schematic description of
Platform: | Size: 203776 | Author: 望天 | Hits:

[Embeded-SCM Develop] signal_tap

Description:
Platform: | Size: 343040 | Author: 钟桂东 | Hits:

[VHDL-FPGA-Verilog] Quartus_II_7.0

Description: Quartus II 7.0工程修复大法。修复不能打开的工程。有人在7.2的软件下用本方法也成功修复。 他是修复这个错误： Error: Can t open project -- you do not have permission to write to all the files or create new files in the project s database directory-Quartus II 7.0 Dafa repair works. Restoration projects can not be opened. It was under the 7.2 software has successfully used this method to repair. He was to repair this error: Error: Can' t open project- you do not have permission to write to all the files or create new files in the project' s database directory
Platform: | Size: 543744 | Author: gan | Hits:

[VHDL-FPGA-Verilog] DE2_SD_Card_Audio

Description: DE2 sopc系统的一个经典应用，希望能够对大家有一定得帮助-DE2 sopc a classic application of the system, hoping to get help to all of us have a certain
Platform: | Size: 18045952 | Author: smolfy | Hits:

[VHDL-FPGA-Verilog] digital_frequency

Description: 用verilog实现数字频率计的设计，具有自动换挡功能，采用t法和m法设计，低频显示周期。量程为0.5~10Mhz。开发环境为quartus-This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
Platform: | Size: 492544 | Author: 孙岩 | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 是在quartus　ＩＩ软件的中编写的ｆｉｆｏ模块的ｖｅｒｉｌｏｇ　ＨＤＬ硬件描述语言代码，提供给大家希望对大家有一定的而帮助。-fjwe fe w w4 twtw43t4 t3fsjs fsd f swefw gewr ge ger g e t 3ewutowj otweu to teow t3o tewr to t3t t3e rtweo t3w 34 t34 o3tjwkl sj ter k.
Platform: | Size: 457728 | Author: 李万林 | Hits:

[VHDL-FPGA-Verilog] Trigger

Description: 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
Platform: | Size: 925696 | Author: baoguocheng | Hits:

[VHDL-FPGA-Verilog] U4

Description: 1、必做：设计并实现一个 8×8 点阵扫描控制器，在点阵上稳定显示一个数字或字母， 颜色红色、绿色均可。 2、选做：用 8×8 点阵显示字符，每次显示一个字符，每秒切换一次，显示内容为“B”、 “U”、“ P”、“T”及姓名的第一个字母。如张三显示的内容为“B”、“U”、“ P”、“ T”、 “Z”、“ S”。(1, must do: design and implement a 8 * 8 dot matrix scanning controller, stable display of a number or letter on the dot matrix, the color is red and green. 2, choose to do: display characters with 8 x 8 dot matrix, display one character each time, switch once a second, display the contents of "B", "U", "P", "T" and the first letter of the name. For example, Zhang San shows the contents of "B", "U", "P", "T", "Z" and "S".)
Platform: | Size: 443392 | Author: 闭家锁的话 | Hits:

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