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Description: quarters2编写的定时器.vhd为源程序-prepared quarters2 timer. vhd for source
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Size: 133120 |
Author: lc |
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Description: vhdl的最简单的加法器，quarters2编译通过-The most simple vhdl adder, quarters2 compiled through
Platform: |
Size: 66560 |
Author: lc |
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Description: 基于VHDL设计的在quarters2上的循环码编码器-VHDL-based design at quarters2 on the cyclic code encoder
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Size: 13312 |
Author: lc |
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Description: 采用verilog语言实现数字钟的编程，quarters2软件环境。-verilog，clock，in quarters2
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Size: 278528 |
Author: Amy |
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