Description: 伪随机序列产生器，VHDL程序，不记得在哪个论坛上下的。-Pseudo-random sequence generator, VHDL procedures, do not remember in which forum from top to bottom. Platform: |
Size: 2048 |
Author:韩丹 |
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Description: 伪随机码发生器的VHDL实现
随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved Platform: |
Size: 217088 |
Author:张之晗 |
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Description: 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded Platform: |
Size: 446464 |
Author:lee |
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Description: 伪随机比特发生器， VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator, Platform: |
Size: 1024 |
Author:阿道夫 |
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Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation. Platform: |
Size: 870400 |
Author:风影 |
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