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Description: An enhanced phase-locked loop (PLL) system is presented
and its properties and performance characteristics
are investigated. Advantages of the proposed PLL
structure over the conventional PLLs including its capability of direct estimation of amplitude and phase angle of its input signal, within a wide range of parameters,are demonstrated. Main features of the proposed PLL are structural simplicity and performance robustness. Performance of the PLL, based on both analog and digital realization, is also presented.
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Size: 418825 |
Author: yangyansky |
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Description: s3c2410 pll 计算程序-computational procedures s3c2410 pll
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Size: 19456 |
Author: 士大夫 |
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Description: The file calculates and plots FM noise sidebands for a carrier. It also does sinusoidal modulation. This simple way of adding noise to a carrier is useful for simulation of PLLs. It turns out, though, that the mean of the randn function is not as close to zero as it could be, and this causes the fft to generate extra sideband energy, which makes it appear as if the noise is not what would be expected. This program gets around this by adding a fudge factor to the randn results to eliminate this problem. It took me ages to figure this out, I hope to reduce a similar effort for others.
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Size: 2048 |
Author: Rafal |
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Description: this the phase locked loops post processer.PLLs are widely used in frequency synthesis, for frequency multipliers and dividers, for carrier and symbol synchronization, and in the implementation of coherent receivers-this is the phase locked loops post processer.PLLs are widely used in frequency synthesis, for frequency multipliers and dividers, for carrier and symbol synchronization, and in the implementation of coherent receivers
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Size: 1024 |
Author: nidhi |
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Description: This a short paper discussing three implementations of digital loop filters for phase-locked loops (PLLs)
implemented either in digital circuitry or in software. This paper is by no means intended to be a
comprehensive theoretical discussion of the topic, but rather a quick reference for the engineering student or
practicing engineer. If you need a theoretical background in the subject of PLLs, please see the
bibliography at the end of this monograph.-This is a short paper discussing three implementations of digital loop filters for phase-locked loops (PLLs)
implemented either in digital circuitry or in software. This paper is by no means intended to be a
comprehensive theoretical discussion of the topic, but rather a quick reference for the engineering student or
practicing engineer. If you need a theoretical background in the subject of PLLs, please see the
bibliography at the end of this monograph.
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Size: 178176 |
Author: parth |
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Description: Phase-Locked Loops
for High-Frequency
Receivers and
Transmitters–Part 2
by Mike Curtin and Paul O’Brien
The first part of this series of articles introduced the basic concepts
of phase-locked loops (PLLs). The PLL architecture and principle
of operation was described and accompanied by an example of
where a PLL might be used in a communication system.
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Size: 89088 |
Author: phitoan |
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Description: The file calculates and plots FM noise sidebands for a carrier. It also does sinusoidal modulation. This simple way of adding noise to a carrier is useful for simulation of PLLs. It turns out, though, that the mean of the randn function is not as close to zero as it could be, and this causes the fft to generate extra sideband energy, which makes it appear as if the noise is not what would be expected. This program gets around this by adding a fudge factor to the randn results to eliminate this problem. It took me ages to figure this out, I hope to reduce a similar effort for others
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Size: 3072 |
Author: zfhou |
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Description: descriptions + helper functions for simple dvb plls.
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Size: 6144 |
Author: xiuchenet |
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Description: PLL: Phase-locked loop
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Size: 852992 |
Author: vilacap15 |
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Description: descriptions + helper functions for simple dvb plls for Linux.
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Size: 6144 |
Author: caimenxan |
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Description: The MST717 is a highquality ASIC for NTSC / P AL car TV application. It receives analog NTSC / P AL CVBS and
S-V ideo inputs from TV tuners, DVD or VCR sources, including weak and distorted signals, as well as analog RGB
input from GPS systems. Automatic gain control (AGC) and 8-bit 3-channel A/D converters provide high
resolution video quantization. With automatic video source and mode detection, users can easily switch and adjust
variety of signal sources. Multiple internal adaptive PLLs precisely extract pixel clock from video source and
perform sharp color demodulation. Built-in line-buffer supports adaptive 2-D comb-filter , 2-D sharpening, and
synchronization stabler in a condense manner . The output format of MST717 supports 6-bit digital TFT -LCD
modules. -The MST717 is a highquality ASIC for NTSC/P AL car TV application. It receives analog NTSC/P AL CVBS and
S-V ideo inputs from TV tuners, DVD or VCR sources, including weak and distorted signals, as well as analog RGB
input from GPS systems. Automatic gain control (AGC) and 8-bit 3-channel A/D converters provide high
resolution video quantization. With automatic video source and mode detection, users can easily switch and adjust
variety of signal sources. Multiple internal adaptive PLLs precisely extract pixel clock from video source and
perform sharp color demodulation. Built-in line-buffer supports adaptive 2-D comb-filter , 2-D sharpening, and
synchronization stabler in a condense manner . The output format of MST717 supports 6-bit digital TFT-LCD
modules.
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Size: 1673216 |
Author: kevap |
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Description: Generate clock using plls.
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Size: 3072 |
Author: binhnhi |
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Description: Get the resulting clock rate a PLL register value and the input frequency. PLLs with this register layout can be found on i.MX1,.
-Get the resulting clock rate a PLL register value and the input frequency. PLLs with this register layout can be found on i.MX1,.
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Size: 16384 |
Author: rvdaibue |
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Description: Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a VCO with 8 channels each, channel 8 is the odd-one-out and does not provide mul div.
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Size: 4096 |
Author: hgvoudz |
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Description: descriptions + helper functions for simple dvb plls.
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Size: 6144 |
Author: tingqkxl |
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Description: The MST717A is a high quality ASIC for NTSC/PAL/SECAM car TV application. It receives analog
NTSC/PAL/SECAM CVBS and S-Video inputs TV tuners, DVD or VCR sources, including weak and distorted
signals, as well as analog RGB input GPS systems. Automatic gain control (AGC) and 8-bit 3-channel A/D
converters provide high resolution video quantization. With automatic video source and mode detection, users
can easily switch and adjust variety of signal sources. Multiple internal adaptive PLLs precisely extract pixel
clock video source and perform sharp color demodulation. Built-in line-buffer supports adaptive 2-D
comb-filter, 2-D sharpening, and synchronization stabler in a condense manner. The output format of
MST717A supports 6-bit or 8-bit TTL digital TFT-LCD modules.-The MST717A is a high quality ASIC for NTSC/PAL/SECAM car TV application. It receives analog
NTSC/PAL/SECAM CVBS and S-Video inputs TV tuners, DVD or VCR sources, including weak and distorted
signals, as well as analog RGB input GPS systems. Automatic gain control (AGC) and 8-bit 3-channel A/D
converters provide high resolution video quantization. With automatic video source and mode detection, users
can easily switch and adjust variety of signal sources. Multiple internal adaptive PLLs precisely extract pixel
clock video source and perform sharp color demodulation. Built-in line-buffer supports adaptive 2-D
comb-filter, 2-D sharpening, and synchronization stabler in a condense manner. The output format of
MST717A supports 6-bit or 8-bit TTL digital TFT-LCD modules.
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Size: 3693568 |
Author: Andrew85 |
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Description: Good source to design PLLs.
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Size: 171008 |
Author: Karou |
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