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[Other resource] 802.16protocol

Description: 1、802．16 协议概述 2 、服务汇聚子层 3、MAC 公共子层 4、加密子层 5、WirelessMAN-OFDM PHY 6、Configuration
Platform: | Size: 2709016 | Author: 孙滔 | Hits:

[DSP program] SEEDVPM642_net_v3.3

Description: SEED-VPM642的以太网接口的测试。主要是测试EMAC 与MDIO 的配置及使用，以及如何设置一个PHY设备和CSL 库中关于网络接口部分程序的应用。在此测试过程中，采用自闭环的方式完成的。-SEED-VPM642 Ethernet interface testing. Mainly EMAC and MDIO test configuration and use, and how to set up a PHY devices and CSL library network interface on the application of some of the procedures. In this testing process, using self-completion of the closed-loop manner.
Platform: | Size: 631808 | Author: peter | Hits:

[VHDL-FPGA-Verilog] MII

Description: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Platform: | Size: 2048 | Author: 雷伟林 | Hits:

[Modem program] wlan_11n_simulink

Description: 802.11n physical layer simulink model-802.11n WLAN PHY Simulation models of 802.11n (modified from 11a PHY model): wlan/IEEE80211n.mdl For all simulation models: -------------------------- Most simulation setting can be configured with the Simulation Settings module in the lower-left portion of the SIMULINK block diagram. The SNR values to test are located in the module directly below, PER Test Settings . Currently, the simulation models are configured for testing a 2x2 antenna configuration, with TGn Channel model D. For testing with an AWGN channel, the file ch_model.m needs to be modified. For testing other channel configurations, the file ch_model_tgn.m should be modified (replace the .mat file tgn_chD_nlos(noflour)_2x2 for load command with other file). Note this file was generated using the "WLAN MIMO Channel Matlab program" by Laurent Schumacher (see references [3], [4] below). Note that most of the other parameters may either be found in the IEEE80211n_settings.m file,
Platform: | Size: 4047872 | Author: scootpeng | Hits:

[ARM-PowerPC-ColdFire-MIPS] hello_emac

Description: 通过本篇，您可以了解到在MicorBlaze系统中如何进行以太网的操作， 包括MAC控制器的配置， PHY的环路测试，以太网数据的发送，接收等方面。-Through this article, you can learn how to make Ethernet in MicorBlaze system operation, including MAC controller configuration, loop test PHY, send the Ethernet data reception, etc..
Platform: | Size: 83968 | Author: ad | Hits:

[Linux-Unix] au1xxx_eth

Description: Platform specific PHY configuration passed to the MAC driver.
Platform: | Size: 1024 | Author: dingxiyang | Hits:

[Linux-Unix] bcm47xxnflash

Description: Platform specific PHY configuration passed to the MAC driver.
Platform: | Size: 3072 | Author: cuijiugp | Hits:

[Linux-Unix] iwl-phy-db

Description: struct iwl_phy_db - stores phy configuration and calibration data.
Platform: | Size: 5120 | Author: flcingsz | Hits:

[Linux-Unix] paravirt_inst

Description: Handle the case where flash memory and ethernet mac phy are mapped onto the same async bank. The BF533-STAMP does this for example. All board-specific configuration goes in your board resources file.
Platform: | Size: 2048 | Author: xanymbx | Hits:

[Linux-Unix] tegra_usb_phy

Description: utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers should be set up by clk-tegra, false if by the PHY code.
Platform: | Size: 1024 | Author: nvsawl | Hits:

[VHDL-FPGA-Verilog] udp_send1

Description: 基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en-UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows: input clk50, input rst_n, /////////////////////// //interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data
Platform: | Size: 53248 | Author: qiubin | Hits:

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