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[Com PortChuanKou

Description: 这是一个汽车压力检测系统,利用RS232串口进行通信,并在可编程并行接口芯片8255A上进行编程,用到了查询方式A/D转换器接口电路及数据采集程序设计原理等-This is a car pressure detection system, using RS232 serial communications and programmable parallel interface 8255A programmable chips, used in the query mode A/D converter interface circuit and data acquisition procedures, such as design principles
Platform: | Size: 3857408 | Author: 方允福 | Hits:

[VHDL-FPGA-VerilogSerialtoParallelConverter

Description: 串行转并行SerialtoParallelConverter-Serial to Parallel SerialtoParallelConverter
Platform: | Size: 26624 | Author: | Hits:

[File FormatAT89C51

Description: 随着微电子技术的不断发展,微处理器芯片的集成程度越来越高,单片机已可以在一块芯片上同时集成CPU、存储器、定时器/计数器、并行和串行接口、看门狗、前置放大器、A/D转换器、D/A转换器等多种电路,这就很容易将计算机技术与测量控制技术结合,组成智能化测量控制系统。这种技术促使机器人技术也有了突飞猛进的发展,目前人们已经完全可以设计并制造出具有某些特殊功能的简易智能机器人。-With the continuous development of microelectronic technology, a microprocessor chip is becoming more integrated, single-chip can simultaneously on a single chip integrated CPU, memory, timer/counter, parallel and serial interface, watchdog , pre-amplifier, A/D converter, D/A converters and other circuits, which it is easy to computer technology and measurement control technology combined to form the intelligent measurement control system. This technology to robot technology has been rapid development, at present has been entirely designed and manufactured with certain special features of the mini-mental robot.
Platform: | Size: 64512 | Author: 林飞 | Hits:

[USB developusb_jtag-20080705-1200

Description: Xilinx USB JTAG 下載端程式 -The jtag_logic.vhd in this directory describes the logic for a parallel-serial converter to be connected to a FT245BM USB chip from FTDI Inc
Platform: | Size: 125952 | Author: simon | Hits:

[VHDL-FPGA-Verilogp2s

Description: 并串转换器:将并行输入的信号以串行方式输出,这里要注意需先对时钟进行分频,用得到的低频信号控制时序,有利于观察结果(可以通过L灯观察结果)-And series converter: the input signal in parallel to serial output, where attention should be paid to the need to carry out first clock frequency, low-frequency signals received by the control timing is conducive to observation (L lamps can be observed)
Platform: | Size: 128000 | Author: 米石 | Hits:

[Otherpar2ser

Description: 并/串转换器即并行输入、串行输出转换器,例如一个8bit输入的并/串转换器,输出时钟频率是输入时钟频率的8倍,输入端一个时钟到来,8个输入端口同时输入数据;输出端以8倍的速度将并行输入的8bit串行输出,至于从高位输出还是从低位输出,可以再程序中指定。-And/or parallel series converter input, serial output converter, for example, a 8bit input and/series converter, the output clock frequency is the input clock frequency of 8 times, the arrival of a clock input, 8 input data input port at the same time output to 8 times the speed of 8bit parallel input serial output, as output from a high level or low output, the procedure can be specified.
Platform: | Size: 1024 | Author: 赵军 | Hits:

[Communication-MobileSoft_demapping_QPSK

Description: soft Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter : needs I and Q components of QPSK symbols at the input
Platform: | Size: 1024 | Author: IMM | Hits:

[Communication-MobileGood_ver_Soft_demapping_QPSK

Description: good version of soft Demapping QPSK : LLR computation using Euclidian distance approache, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
Platform: | Size: 1024 | Author: IMM | Hits:

[matlabSoft_demapping_8PSK

Description: soft Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of 8PSK symbols at the input
Platform: | Size: 1024 | Author: IMM | Hits:

[Communication-Mobiledemapping_soft_QPSK_good_version

Description: corrected version of Demapping QPSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, needs I and Q componets of QPSK symbols at the input
Platform: | Size: 1024 | Author: IMM | Hits:

[matlabHard_decision_demapping_8PSK

Description: Demapping 8PSK : LLR computation using Euclidian distance approach, Parallel-to-Serial converter, Hard decision, needs I and Q componets of 8PSK symbols at the input
Platform: | Size: 1024 | Author: IMM | Hits:

[matlabs2p

Description: serial to parallel converter
Platform: | Size: 6144 | Author: mon | Hits:

[VHDL-FPGA-VerilogP_to_ser

Description: parallel to serial data converter using VHDL
Platform: | Size: 98304 | Author: tg | Hits:

[VHDL-FPGA-VerilogSerpar

Description: A serial to parallel converter is somewhat the reverse of the operation of parallel to serial converter. The data comes serially from the input port SERIN. The parallel data is output from DOUT port. Output port DRDY is asserted ‘1’ when the start bit, 8 bit data and the parity bit is received. Output port PERRn is asserted ‘0’ when the parity bit received is different from the parity generated inside the serial to parallel circuit. When parity error is detected, the serial to parallel circuit would be reset before its normal operation can be performed. This is the operation for serial to parallel module.
Platform: | Size: 1024 | Author: riadh | Hits:

[VHDL-FPGA-VerilogSERIALIZER

Description: The serial bit stream is clocked out of the Parallel-to-Serial converter .
Platform: | Size: 1024 | Author: Nikhil | Hits:

[Software EngineeringVLSI

Description: The AD7654 is a low cost, simultaneous sampling, dual-channel, 16-bit, charge redistribution SAR, analog-to-digital converter that operates from a single 5 V power supply. It contains two low noise, wide bandwidth, track-and-hold amplifiers that allow simultaneous sampling, a high speed 16-bit sampling ADC, an internal conversion clock, error correction circuits, and both serial and parallel
Platform: | Size: 3964928 | Author: vxl | Hits:

[OtherP2S

Description: Parallel to Serial converter Module
Platform: | Size: 2048 | Author: hadimk | Hits:

[VHDL-FPGA-Verilogseria-to-parallel

Description: 主要用来实现数据串并转换功能,内附2种实现程序-serial to parallel converter verilog code
Platform: | Size: 1024 | Author: 徐以为 | Hits:

[VHDL-FPGA-Verilogp-s

Description: this the code for parallel to serial converter-this is the code for parallel to serial converter
Platform: | Size: 1024 | Author: RHS | Hits:

[VHDL-FPGA-VerilogParallel-To-Serial-Converter

Description: Verilog Module for 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registers with Clock Enable and Asynchronous Clear
Platform: | Size: 148480 | Author: Raz | Hits:
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