Description: 用vhdl代码写的并行转串行的程序,波形图正确,已经在板子上运行过,良好-using VHDL code written in parallel to serial procedures waveform correct, the board has been running that good Platform: |
Size: 99367 |
Author:国宝 |
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Description: 这是一个用VHDL语言编写的并口转串口程序，在altera开发系统下验证通过，运用于开发板与计算机之间的通信，源程序可以提供参考-This is a use of the VHDL language Parallel to Serial procedures, In altera development system under test passed, the development of applied between the panels and computer communications, can provide a reference source Platform: |
Size: 1196 |
Author:华涛 |
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Description: dsp5416与tl16c550实现并口转串口通信程序-dsp5416 with tl16c550 achieve Parallel to Serial Communication Program Platform: |
Size: 20585 |
Author:金鹤 |
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Description: 并口开发实用工具的文档和源码，已根据此开发出并口调试I2C的实用工具。-Parallel to the development of practical tools and source files, this has developed parallel debugging I2C a practical tool. Platform: |
Size: 4134912 |
Author:田 |
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Description: CH341评估板，演示USB转串口、转打印口、转并口及同步串口等-CH341 Evaluation and demonstration USB to serial, LPT switch, switch synchronous serial port and parallel port, etc. Platform: |
Size: 740352 |
Author:永 |
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Description: 这是一个汽车压力检测系统，利用RS232串口进行通信，并在可编程并行接口芯片8255A上进行编程，用到了查询方式A/D转换器接口电路及数据采集程序设计原理等-This is a car pressure detection system, using RS232 serial communications and programmable parallel interface 8255A programmable chips, used in the query mode A/D converter interface circuit and data acquisition procedures, such as design principles Platform: |
Size: 3857408 |
Author:方允福 |
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Description: 该模块主要完成并串转换功能。其中system_clk是输入并行时钟的频率，它是串行时钟serial_clk的八倍。byte_data_en是输入并行数据使能信号，byte_data是输入并行数据。serial_data是转换后的串行数据，bit_data_enable是串行数据有效信号。-The module main is completed and the string conversion functions. System_clk which is an input parallel clock frequency, it is the serial clock serial_clk eight times. byte_data_en is a parallel data input enable signal, byte_data is a parallel data input. serial_data is converted serial data, bit_data_enable is the serial data signal. Platform: |
Size: 1024 |
Author:huangdecheng |
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Description: 一个并行转串行的verilog源程序,可以讲12位并行数据转换为一个串行数据-A parallel to serial verilog source code you can transfer your parallel data to serial data.you have 12bits parallel data then you will have a serial data Platform: |
Size: 153600 |
Author:梅博 |
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Description: 并行和串行级联码已成为一种实用的方法，取得了良好的性能。在此论文中，我们将介绍并行和串行级联单奇偶校验乘积码。我们对这种码的码重分布进行了分析，其性能是有界的。仿真的结果确定了在高信噪比情况下的性能界限。这种码（与一些变种）的性能证明对于降低译码复杂性和适当的短码长具有相当良好的效果。-Parallel and serial concatenated code has become a practical way to obtain good performance. In this paper, we will introduce the parallel and serial concatenated single parity check product codes. We re-distribution of this code code analysis, and its performance is bounded. The results of the simulation to determine the performance limits in the case of a high signal-to-noise ratio. Proof of performance of this code (with some variants) having a fairly good effect for reducing the decoding complexity and the appropriate short code length. Platform: |
Size: 496640 |
Author:moulight |
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Description: This page of VHDL source code covers 2 bit parallel to serial vhdl code and provides link to 2 bit serial to parallel conversion. Platform: |
Size: 1024 |
Author:ss |
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Description: 用Verilog语言编程实现并行转串行，并在modelsim中仿真出波形。-programming to realize parallel to serial using Verilog language , and simulating waveform in the modelsim. Platform: |
Size: 1024 |
Author:宁倩慧 |
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