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[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 951 | Author: 李兵 | Hits:

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms
Platform: | Size: 2048 | Author: 李丹 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个用verilog编的时钟程序A clock with the procedures for verilog-A clock with verilog program for A clock with the procedures for verilog
Platform: | Size: 295936 | Author: lee | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
Platform: | Size: 571392 | Author: alvin | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: verilog代码，跑表计数器程序， 希望能帮到感兴趣的人~-verilog code run led
Platform: | Size: 1024 | Author: tulip | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 用verilog 编写的数码管显示的秒表-Prepared using verilog digital display of stopwatch
Platform: | Size: 1015808 | Author: eagleli | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 该程序是用verilog语言实现的数字跑表功能，其中分为计数模块与数码管显示模块。-The program is verilog language digital stopwatch function, which is divided into counting module with digital display module.
Platform: | Size: 1024 | Author: 柳庆勇 | Hits:

[VHDL-FPGA-Verilog] paobiao-_verilog

Description: 数字跑表，硬件表述语言Verilog 实现，测试功能全 -Digital stopwatch, expression language Verilog hardware implementation, testing, full-featured
Platform: | Size: 156672 | Author: myname | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 这个程序是用verilog语言下的数字跑表实验，经测试，好用。-This program is a digital stopwatch experiments under the verilog language, tested, easy to use.
Platform: | Size: 5120 | Author: zheqi | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 本源码是用verilog编写的FPGA程序，其中包括了数字跑表模块和RS触发器模块。-The source code is written in verilog FPGA programs, including digital stopwatch module and the RS flip-flop modules.
Platform: | Size: 1024 | Author: 黄华 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
Platform: | Size: 165888 | Author: 天王 | Hits:

[Other] paobiao

Description: verilog实现数码跑表，基于ALTERA DE2—70开发板实现验证，其中代码不分模块。-verilog achieve digital stopwatch, to achieve certification based ALTERA DE2-70 development board, regardless of where the code module.
Platform: | Size: 491520 | Author: 王亚斌 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 使用verilog实现跑表计时功能,已经验证过，能够实现功能-Use verilog to achieve run time function
Platform: | Size: 17112064 | Author: yang | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 此上传的是在FPGA的spartan 3e系列开发板上面实现精准到 时、分、秒、百分秒的数字跑表的Verilog源代码。(This is uploaded on the FPGA Spartan 3E series development board to achieve precise time, minute, seconds, 100 seconds of digital stopwatch Verilog source code.)
Platform: | Size: 15143936 | Author: 木子桶 | Hits:

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