Description: A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation.
-A gate level implementation of a Booth Encoded Radix-4 24 bit multiplier with VHDL code in structural form. Carry-save adder and hierarchical CLA adder is used for the component adders in the design. The 12 partial products is a Wallace Adder Tree built from Carry-save adder using 3 to 2 reduction. A hierarchical CLA ( Carry-look-Ahead Adder ) adder is used for the final product generation. Platform: |
Size: 7168 |
Author:Michael Lee |
Hits:
Description: The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one.-The Vedic mathematics is quite different from
conventional method of multiplication like adder and shifter.
This mathematics is mainly based on sixteen principles. The
multiplier (referred henceforth as Vedic multiplier)
architecture based on the URDHVA TIRYAKBHYAM
(Vertically and cross wise) sutra is presented. The existing
method is 16*16 bit multiplication in relatively less speed. The
proposed method is 32*32 bit multiplication in terms of
relatively high speed, low power, less area and less delay. This
will help in designing multiplier in VHDL, as its give effective
utilization of structural method of modelling. This also gives
chances for modular design where smaller block can be used to
design the bigger one. Platform: |
Size: 172032 |
Author:farbosein |
Hits:
Search - multiplier structural