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[VHDL-FPGA-VerilogLPT

Description: 实现开漏输出的并口,支持3.3V或5V,支持FPGA 的PS 配置功能。8位配置数据 自动移位输出,输入时钟24MHz,产生1MHz配置时钟。8位CPU数据总线接口, 11位地址总线。支持IO 的置位清除功能。-The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
Platform: | Size: 2048 | Author: tianrongcai | Hits:

[OtherunIPROGV_VHDL

Description: Universal LPT programmer on VHDL
Platform: | Size: 2048 | Author: Kota | Hits:

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