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Description: 1）通过fs44b0xbios和网口，将upload里的boot.bin烧写到flash 0 地址
见“FS44B0Xbios使用指南”之5
2) 打开57600超级终端
3) 连上串口线和jtag调试头
4）打开FS44B0X开发板电源
5）运行jtag.exe,在SDT下调入 ucosii_demo.axf，运行
6) 在超级终端上有三个任务的运行与退出显示，板子上的三个发光二极管会来回闪烁。
-a) fs44b0xbios and LAN, li will upload the burning of flash boot.bin 0 addresses see "FS44B0Xbio s User's Guide "5 2) to open 57,600 Super Terminal 3) connected to serial lines and the first four JTAG Debugging) Open FS44B0X development board Power 5) Run jtag.exe, under the redeployment ucosii_demo.axf SDT, running 6) of the Super Terminal 3 on the mandate of the operation and withdraw from the show, on board the three light-emitting diodes will flicker back and forth.
Platform: |
Size: 215299 |
Author: 张淼林 |
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Description: MSP430-JTAG-Adapter:MSP430-JTAG doesn’t need external power supply, as MSP430 microcontrollers require only 3-5 mA while programming and all necessary
power supply is taken from the LPT port.-MSP430 - JTAG-Adapter : MSP430 - JTAG does not need external power supply, as MSP430 microcontrollers require only 3-5 mA while programming and all necessary power supply is taken from the LPT port.
Platform: |
Size: 811557 |
Author: 王晗 |
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Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。
以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。
-JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: |
Size: 2023 |
Author: 李伟 |
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Description: 上传一个arm调试软件，在xp下调试jtag经常出错，推荐使用该软件比较好用。-upload an arm debug software, under the xp JTAG Debugging often wrong, Suggested use the software more user friendly.
Platform: |
Size: 960459 |
Author: 董伟 |
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Description: 第4章 应用系统设计
4.1 系统设计概述
4.2 ARM920T简介
4.3 S3C2410X处理器详解
4.4 单元电路设计
4.5 存储器系统设计
4.6 JTAG调试接口设计
4.7 综合训练之通过JTAG访问外设
Platform: |
Size: 1911798 |
Author: zhang |
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Description: JTAG Tools is a software package which enables working with JTAG-aware
(IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter.
Platform: |
Size: 466107 |
Author: pavel |
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Description: 编写一个延时1MS子程序根据题目选择是定时还是记数状态，本题选择记数状态。然后根据延时1MS计算出计时器的初值是E0H（高8位）18H（低5位）。最后编写算法，对T0初始化，利用T0的中断TF0调用中断处理程序。-prepared a delay rungs subroutine under the topic chosen is not a time to memorize numbers or state of mind of the few options that state. According to delay timer rungs calculate the initial value is E0H (high 8) 18H (Low 5). Preparation of the final algorithm, the T0 initialization, interrupt the use of T0 TF0 call interrupt handling procedures.
Platform: |
Size: 3072 |
Author: 李明 |
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Description: MSP430-JTAG-Adapter:MSP430-JTAG doesn’t need external power supply, as MSP430 microcontrollers require only 3-5 mA while programming and all necessary
power supply is taken from the LPT port.-MSP430- JTAG-Adapter : MSP430- JTAG does not need external power supply, as MSP430 microcontrollers require only 3-5 mA while programming and all necessary power supply is taken from the LPT port.
Platform: |
Size: 811008 |
Author: 王晗 |
Hits:
Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。
以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。
-JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: |
Size: 2048 |
Author: 李伟 |
Hits:
Description: 上传一个arm调试软件，在xp下调试jtag经常出错，推荐使用该软件比较好用。-upload an arm debug software, under the xp JTAG Debugging often wrong, Suggested use the software more user friendly.
Platform: |
Size: 960512 |
Author: 董伟 |
Hits:
Description: ％ [BestPop,Trace]=fmaxga(FUN,LB,UB,eranum,popsize,pcross,pmutation)
％ Finds a maximum of a function of several variables.
％ fmaxga solves problems of the form:
％ max F(X) subject to: LB <= X <= UB
％ BestPop--------最优的群体即为最优的染色体群
％ Trace----------最佳染色体所对应的目标函数值
％ FUN------------目标函数
％ LB-------------自变量下限
％ UB-------------自变量上限
％ eranum---------种群的代数,取100--1000(默认1000)
％ popsize--------每一代种群的规模；此可取50--100(默认50)
％ pcross---------交叉的概率,此概率一般取0.5--0.85之间较好(默认0.8)
％ pmutation------变异的概率,该概率一般取0.05-0.2左右较好(默认0.1)
％ options--------1×2矩阵,options(1)=0二进制编码(默认0),option(1)~=0十进制编码,option(2)设定求解精度(默认1e-4)- [BestPop, Trace] = fmaxga (FUN, LB, UB, eranum, popsize, pcross, pmutation) Finds a maximum of a function of several variables. Fmaxga solves problems of the form: max F (X) subject to : LB <= X <= UB BestPop-------- optimal chromosome groups is the best group Trace---------- chromosome corresponding to the best objective function value FUN------------ objective function LB------------- variable lower limit since the UB------------- variable upper limit eranum--------- populations algebra, take 100- 1000 (default 1000) popsize-------- population size of each generation this desirable 50- 100 (default 50) pcross--------- crossover probability, the probability of a general check 0.5- 0.85 between the better (default 0.8) pmutation------ mutation probability, the probability of 0.05 general admission better about-0.2 (default 0.1) options-------- 1 × 2 matrix, options (1) = 0 binary code (default 0), option (1) ~ = 0 decimal coding, option (2 ) set accuracy (default 1e-4)
Platform: |
Size: 3072 |
Author: mmcc |
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Description: 第4章 应用系统设计
4.1 系统设计概述
4.2 ARM920T简介
4.3 S3C2410X处理器详解
4.4 单元电路设计
4.5 存储器系统设计
4.6 JTAG调试接口设计
4.7 综合训练之通过JTAG访问外设
-Chapter 4 Application System Design System Design overview 4.1 Introduction 4.2 ARM920T processor 4.3 S3C2410X unit 4.4 Detailed Circuit Design System 4.5 Memory 4.6 JTAG debug interface design 4.7 Comprehensive training visit peripherals through the JTAG
Platform: |
Size: 1911808 |
Author: zhang |
Hits:
Description: JTAG Tools is a software package which enables working with JTAG-aware
(IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter.
Platform: |
Size: 465920 |
Author: pavel |
Hits:
Description: flash programming STI 5.5.1.4 DCU3
Platform: |
Size: 3349504 |
Author: Yves |
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Description: 通过jtag口写BF532（AD BlackFin CPU)的代码。-Program to write flash for BF532 Blackfin CPU.
Platform: |
Size: 583680 |
Author: ali |
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Description: urjtag source jtag for sti stb procesor
Platform: |
Size: 314368 |
Author: mi |
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Description: introduction to jtag and boundary scan
Platform: |
Size: 916480 |
Author: devil412 |
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Description: FPGA配置,CPS4,AS MODE,PS MODE, JTAG MODE -FPGA config
Platform: |
Size: 158720 |
Author: 陈澄 |
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Description: JTAG防锁死和LM3S系列几个基本例程-arm jtag unlock
Platform: |
Size: 195584 |
Author: adam |
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Description: JTAG边界扫描测试技术原理，JTAG边界扫描测试技术原理-JTAG boundary-scan test technology principle, JTAG boundary-scan test technology principle
Platform: |
Size: 720896 |
Author: 李 |
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