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[Other resource] 8x8IDCT

Description: 8x8 iDCT verilog code 一次輸入八個點
Platform: | Size: 8304248 | Author: Emuil | Hits:

[Graph program] xapp208

Description: xilinx 基于查找表方法实现的IDCT的verilog源码
Platform: | Size: 8786 | Author: lee | Hits:

[Graph program] DCT-vhdl

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Platform: | Size: 10240 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] 8x8IDCT

Description: 8x8 iDCT verilog code 一次輸入八個點-8x8 iDCT verilog code once the importation of eight points
Platform: | Size: 8303616 | Author: Emuil | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: 离散余弦变换及反离散余弦变换的HDL代码及测试文件。包括VHDL及Verilog版本。可用途JPEG及MEPG压缩算法。-Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Platform: | Size: 29696 | Author: caesar | Hits:

[Graph program] xapp208

Description: xilinx 基于查找表方法实现的IDCT的verilog源码-Xilinx LUT-based method to achieve the IDCT of the Verilog source code
Platform: | Size: 8192 | Author: lee | Hits:

[mpeg mp3] mpeg2_idct_hw

Description: 2-D的DCT/IDCT在軟硬體上的verilog code-dct/idct source code for soc
Platform: | Size: 10801152 | Author: 陳伯綸 | Hits:

[VHDL-FPGA-Verilog] IDCT

Description: 用verilog HDL语言编写的IDCT程序，可以计算8*8的整形数矩阵，用ISE 9.1i编译通过-Using verilog HDL language of the IDCT program can calculate the number of 8* 8 matrix of plastic, with ISE 9.1i compiled by
Platform: | Size: 479232 | Author: 阿文 | Hits:

[Compress-Decompress algrithms] DCTPROGRAM.ZIP

Description: it is verilog code for two dimentional dct
Platform: | Size: 18432 | Author: suhu | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: verilog code for DCT and IDCT (JPEG)
Platform: | Size: 63488 | Author: Dang Tien Dat | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: H264/AVS中的离散余弦变换DCT以及反离散余弦变换IDCT的Verilog代码-H264/AVS the discrete cosine transform and inverse discrete cosine transform DCT IDCT of Verilog code
Platform: | Size: 28672 | Author: 李柏祥 | Hits:

[VHDL-FPGA-Verilog] dctidct

Description: dct and idct code for verilog
Platform: | Size: 2048 | Author: kartik | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[Graph program] xapp208

Description: xilinx 基于查找表方法实现的IDCT的verilog源码-Xilinx LUT-based method to achieve the IDCT of the Verilog source code
Platform: | Size: 9216 | Author: ening | Hits:

[VHDL-FPGA-Verilog] IDCT

Description: HEVC是正在研发的新一代视频编码标准。 本文面向HDTV应用，设计兼容HEVC标准的两位整数IDCT电路， 通过对IDCT的特点进行分析，完成了电路的架构设计, 采用较为节省面积的做法和流水线结构，并进行VerilogHDL代码设计-High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architecture based on HEVC is presented. By the analysis of the architecture design and adopting the area-saved and pipelined one, the Verilog HDL code is designed as well as logical simulation and performance analysis.
Platform: | Size: 5120 | Author: 毕翔宇 | Hits:

[VHDL-FPGA-Verilog] DCT_IDCT

Description: DCT and Idct with vhdl and verilog
Platform: | Size: 62464 | Author: lovers2015 | Hits:

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