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[Other resource] 用Verilog HDL实现I2C总线功能

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Platform: | Size: 121607 | Author: 胡路听 | Hits:

[Other resource] I2C总线控制器 Xilinx提供

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Platform: | Size: 889991 | Author: 司法 | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212859 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] 用Verilog HDL实现I2C总线功能

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-with Verilog HDL I2C bus function of I2C bus is very helpful
Platform: | Size: 120832 | Author: 胡路听 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 Xilinx提供

Description: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Platform: | Size: 889856 | Author: 司法 | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212992 | Author: 李浩 | Hits:

[Embeded-SCM Develop] an494_design_example

Description: I2C to GPIO Port expander的Verilog HDL 程序原码，直接可在Quartus环境下运行。-I2C to GPIO Port expander procedures of the Verilog HDL source code directly in the Quartus environment.
Platform: | Size: 279552 | Author: wangyunshann | Hits:

[VHDL-FPGA-Verilog] I2C(VHDLVerilogHDL)

Description: 有两个，一个用VHDL编写的I2C，一个Verilog hdl语言编写的-Have two, one with VHDL prepared I2C, a Verilog hdl languages
Platform: | Size: 514048 | Author: sunstar | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 用verilog HDL实现I2C Master Controller 的设计，包括主程序设计和测试程序设计-Verilog HDL using I2C Master Controller to achieve the design, including the main program design and test program design
Platform: | Size: 211968 | Author: zbs | Hits:

[Other Embeded program] I2C19861208888

Description: i2c总线模拟，verilog hdl编写的总线模拟控制程序-i2c bus simulation, verilog hdl prepared bus analog control procedures
Platform: | Size: 11264 | Author: 韩永高 | Hits:

[Other] i2c.tar

Description: I2C verilog HDL code including test environment
Platform: | Size: 702464 | Author: richman | Hits:

[Embeded-SCM Develop] i2_cmaster

Description: verilog HDL i2c主机代码-verilog HDL i2c host code
Platform: | Size: 1024 | Author: 李爱国 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: I2C主机端模块 具有avalon-MT总线接口 可挂载在Altera soc系统之上 使NiosII处理器具备I2C通信能力 模块由Verilog HDL编写 并经Cyclone II FPGA测试-I2C master modul which has a avalon-MT interface that can be attached to Altera SOC system. It provides NiosII I2C communication capability . This module is written with Verilog HDL and has been tested on a Cyclone II FPGA
Platform: | Size: 6144 | Author: magic_andy | Hits:

[VHDL-FPGA-Verilog] i2c

Description: verilog hdl file i2c interfacing-verilog hdl file i2c interfacing
Platform: | Size: 2048 | Author: ved prakash | Hits:

[Software Engineering] i2c.tar

Description: i2c core for verilog hdl
Platform: | Size: 647168 | Author: mona | Hits:

[VHDL-FPGA-Verilog] i2c

Description: 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl
Platform: | Size: 3072 | Author: wangminghui | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 本源代码中用Verilog HDL语言编写了I2C的顶层及子模块文件，详细完整，并在Altera实验板上得以验证-primitive code discribe the I2C s function using the Verilog HDL language, the code are particular and integrity,moreover it has been validated in the altera FPGA and passed
Platform: | Size: 18432 | Author: 蔡德胜 | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] I2C

Description: I2C的Verilog HDL简单学习程序-The Verilog HDL simple I2C learning process
Platform: | Size: 2048 | Author: 石成金 | Hits:

[hardware design] i2c_ctrl_master1

Description: I2C总线控制器，master端，控制寄存器读写(I2C Master controller)
Platform: | Size: 1024 | Author: 哈哈鱼 | Hits:
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