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Description: VHDL实现四位全加器，适合初学者，源程序下载-VHDL realization of four full adder, suitable for beginners, the source code download
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Size: 112640 |
Author: 黄利 |
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Description: 一位全加器可由两个一位半加器与一个或门构成，该设计利用层次结构描述法，首先设计半加器电路，将其打包为半加器模块；然后在顶层调用半加器模块组成全加器电路-A full adder can be two a half-adder and an OR gate structure, the design is the use of hierarchical description method, first of all the design half-adder circuit, be packaged as a half-adder module and then call at the top half-adder composed of full-adder circuit modules
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Size: 157696 |
Author: 哈哈 |
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Description: 四位全加器的集成版图设计，基于tanner软件平台的layout设计，欢迎下载-The integration of four full adder layout, tanner software platform based on layout design, please download
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Size: 6144 |
Author: 杨川 |
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Description: 1.八进制计数器
2.八位右移寄存器
3.八位右移寄存器（并行输入串行输出）
4.半加
5.半加器
6.半减器
7.两数比较器
8.三数比较器
9.D触发器
10.T触发器
11.JK1触发器
12.JK触发器
13.三位全加器
14.SR触发器
15.T1触发器
16.三太门
17.有D触发器构成的6位2进制计数器
18.带同步置数的7进制减法计数器（6位右移寄存器）
19.二十四进制双向计数器
20.二选一
21.分频器
22.含同步清零的十进制加计数器
23.或门
24.7段译码器
25.8-3优先编码器
26.32位锁存器
27.八位左移寄存器
28.数据选择器4选1
29.两个三位二进制数全加器
-1 octal counter 2. Eight right register 3. Eight right register (parallel input serial output) 4 and a half plus 5 half adder 6. Half 7. Comparator compares the two numbers 8 Third number is 9.D trigger 10.T trigger 11.JK1 trigger 12.JK trigger 13. three full adder 14.SR trigger 15.T1 trigger 16. three too gate 17 with a D flip-flops 6-bit binary counter 18. 7 binary down counter with synchronous set number (6 right shift register) 19. twenty-four bidirectional binary counter 20. Alternative 21. divider 22. including synchronous clear plus zero decimal counter 23., or 24.7 Doors segment decoder 25.8-3 Priority Encoder 26.32 latch 27. eight left shift register 28. 4 election data selector 129. two three binary full adder implement
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Size: 4096 |
Author: wanghao |
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