Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fpga dpram

Search list

[Other resource] asyrw

Description: C6713dsp to fpga dpram,自己调试成功了，交换万岁
Platform: | Size: 1807 | Author: 丁科 | Hits:

[VHDL-FPGA-Verilog] dpram_fpga

Description: 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
Platform: | Size: 2831360 | Author: 李伟 | Hits:

[DSP program] asyrw

Description: C6713dsp to fpga dpram,自己调试成功了，交换万岁-C6713dsp to fpga dpram, debug their successful, long live exchange
Platform: | Size: 2048 | Author: 丁科 | Hits:

[VHDL-FPGA-Verilog] DPRAM

Description: 利用vhdl编写的双端口Ram程序，不带数据纠错处理-VHDL prepared to use dual-port Ram procedures, do not deal with data error correction
Platform: | Size: 1024 | Author: 孙敬辉 | Hits:

[VHDL-FPGA-Verilog] dpram

Description: FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
Platform: | Size: 352256 | Author: hzh | Hits:

[VHDL-FPGA-Verilog] dpramcore

Description: 基于altera fpga的dpram ipcore 设计，包含整个工程和modelsim仿真文件。读写地址及读写使能是通过数据产生模块来产生。-Altera fpga dpram ipcore design, including engineering and modelsim simulation file. Read and write address and read and write is through the data module.
Platform: | Size: 28038144 | Author: ghj | Hits:

[DSP program] RS2322

Description: verilog 功能：DSP或单片机向FPGA的DPRAM中写入一块数据（最大不超过2K字节,前2个字节为代发送数据长度），然后给出启动信号send_start，本模块自动读出DPRAM中的数据，按设定的波特率将DPRAM中规定的长度的数据发送出去。 接口信号说明： send_start：启动FPGA串行发送脉冲 sys_rst：系统复位脉冲 bps_setup：波特率选择 clk5_714：5.714MHz时钟 char_in：从DPRAM中读出的代发送数据 ReadPtr_w：DPRAM读指针 charout：串行数据输出 bps_clk：位时钟（测试用） SendFlag:发送标志（发送数据时为1） 开发环境：ISE8.4-verilog functions: DSP or microcontroller to the DPRAM of the FPGA to write a data (no more than 2K bytes, the first two bytes on behalf of the send data length), then gives the start signal send_start, this module automatically read the DPRAM data, set the baud rate specified in the DPRAM length of data sent. Interface signals Description: the send_start: Start FPGA serial send the pulse sys_rst: system reset pulse bps_setup: baud rate selection clk5_714: the 5.714MHz clock char_in: DPRAM read out on behalf of the sending data ReadPtr_w: the DPRAM Reading the pointer charout: serial data output bps_clk: SendFlag bit clock (test): Send logo (send data to 1)
Platform: | Size: 1024 | Author: 胡铁乔 | Hits:

[Documents] 基于Actel-FPGA-的双端口RAM-设计

Description: 基于Actel-FPGA-的双端口RAM-设计(Base Actel-FPGA-Dual Port Ram design)
Platform: | Size: 270336 | Author: lysir | Hits:

CodeBus www.codebus.net