Welcome![Sign In][Sign Up]
Location:
Search - fpga 20M 96

Search list

[VHDL-FPGA-VerilogUART

Description: 输入时钟20M,波特率为9600,实现串口收发功能,通过修改内部分频系数可实现其它波特率的收发-Input clock 20M, the baud rate for 9600, Serial transceiver functions, by modifying the frequency of some other baud rate coefficient can realize the transceiver
Platform: | Size: 7168 | Author: 杨启勇 | Hits:

CodeBus www.codebus.net