Description: 6级流水,verilog实现浮点数的加法,其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard Platform: |
Size: 2048 |
Author:兰兰 |
Hits:
Description: 一个32位元的浮点数加法器,可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value Platform: |
Size: 10240 |
Author:TTJ |
Hits:
Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved! Platform: |
Size: 278528 |
Author:王强 |
Hits:
Description: 该代码描述了一个浮点加法器的功能,浮点格式采用IEEE标准-The code describes a floating-point adder function, the use of IEEE standard floating-point format Platform: |
Size: 1024 |
Author:钟毓秀 |
Hits:
Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder. Platform: |
Size: 154624 |
Author:凌音 |
Hits:
Description: GUI方法的浮点数加法器实例,运用了textfield和button-GUI method of floating-point adder instance, use the textfield and the button Platform: |
Size: 1024 |
Author:龚恺 |
Hits: