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Description: 256点FFT IP核。包括16bit和8bit两种精度和C、VHDL、Verilog三种语言的多版本、多精度的IP核
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Size: 352372 |
Author: ykletter@163.com |
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Description: 512点FFT IP核。包括C、VHDL和Verilog三种语言版本,8bit与16bit两种精度。
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Size: 410745 |
Author: ykletter@163.com |
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Description: 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
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Size: 2048 |
Author: lsd |
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Description: 在Altera芯片2C35F672平台上的FFT程序,采用DSPBuilder5.0,生成Verilog文件。开发环境:QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
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Size: 474112 |
Author: lovenevol |
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Description: 这是一个fft的IP核,安装要求为quartus6.0以上。解压安装后可在quartus里例化使用,元件主要为cyclone和stratix,最大支持1024点的转换。
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Size: 8719360 |
Author: 李杰 |
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Description: 128点fft的IP核vhdl源代码,另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
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Size: 7168 |
Author: 戈立军 |
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Description: 对vga接口做了详细的介绍,并且有一
·三段式Verilog的IDE程序,但只有DMA
·电子密码锁,基于fpga实现,密码正
·IIR、FIR、FFT各模块程序设计例程,
·基于逻辑工具的以太网开发,基于逻
·自己写的一个测温元件(ds18b20)的
·光纤通信中的SDH数据帧解析及提取的
·VHDL Programming by Example(McGr
·这是CAN总线控制器的IP核,源码是由
·FPGA设计的SDRAM控制器,有仿真代码
·xilinx fpga 下的IDE控制器原代码,
·用verilog写的,基于查表法实现的LO
·精通verilog HDL语言编- up:in STD_LOGIC
down:in STD_LOGIC
run_stop:in STD_LOGIC
wai_t: in std_logic_vector(2 downto 0)
lift:in std_logic_vector(2 downto 0)
ladd: out std_logic_vector(1 downto 0)
)
end control
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Size: 18683904 |
Author: liuzhou |
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Description: FFT IP core 源码 状态控制机-FFT IP core
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Size: 7168 |
Author: chris |
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Description: verilog实现的FFT变换,经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
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Size: 618496 |
Author: culun |
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Description: 基于IP核的FPGA FFT算法模块的设计与实现
在QUATUSII下实现-IP-based core module FPGA FFT algorithm design and implementation be achieved in QUATUSII
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Size: 222208 |
Author: linxing |
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Description: 利用IP Core编写的Verilog程序,实现FFT变换,希望对大家有帮助。-Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.
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Size: 99328 |
Author: chengyungang |
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Description: VERILOG FFT IP核调用,以及其控制文件-VERILOG FFT IP core call, as well as its control file
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Size: 20978688 |
Author: 贾斌 |
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Description: verilog 实现FFT IP核的控制,借鉴给需要学习的朋友-verilog achieve FFT IP core control, reference to the need to learn a friend
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Size: 12124160 |
Author: 甘超 |
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Description: verilog实现的FFT变换,经硬件测试其功能与AAltera的FFT IP核相近,
-verilog realization of the FFT algorithm, its function is similar to the FFT IP AAltera the nuclear test by the hardware,
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Size: 619520 |
Author: magnet |
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Description: altera公司fft ip核的运用。语言是verilog.-Altera company s fft ip. Language verilog.
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Size: 11977728 |
Author: shiyuan |
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Description: FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
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Size: 8192 |
Author: liu |
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Description: ALTERA的FFT IP核时序的仿真,verilog语言。采用burst方式,FFT点数2048点-FFT IP core of timing simulation ALTERA, verilog language. Using burst mode, FFT points 2048 points
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Size: 25623552 |
Author: vincentspace |
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Description: Verilog,关于如何调用Altera官方的FFT iP核,如何输入和得到输出的实例。
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Size: 9807 |
Author: dumn1234 |
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Description: verilog xilinx IP实现FFT仿真-Verilog xilinx IP implementation FFT simulation
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Size: 2973696 |
Author: 欧阳 |
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Description: IP core fft verilog code example
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Size: 5766144 |
Author: mrv
|
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