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[VHDL-FPGA-Verilogfarrow

Description: 一份很好的数字时延程序(采用farrow算法),采用Verilog HDL,经过测试通过,是我一个雷达项目中的代替模拟时延的。精度很高,并有MATLAB程序验证-A good digital delay, Verilog HDL, procedures, is my test through a radar simulation project instead of the delay. Precision is high, and MATLAB validation
Platform: | Size: 7234560 | Author: 左洪成 | Hits:

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