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[VHDL-FPGA-Verilog多功能电子钟

Description: 具有多种功能的电子钟:闹钟,报时和修改,定时闹钟,报时时间,带闹钟,报时开关。-with multiple functions of electronic bell : alarm clock, timer and modification, regular alarm clock, timer, with alarm clock, timer switches.
Platform: | Size: 6144 | Author: 张建 | Hits:

[SCMclock

Description: 电子闹钟 clk: 标准时钟信号,本例中,其频率为4Hz; clk_1k: 产生闹铃音、报时音的时钟信号,本例中其频率为1024Hz; mode: 功能控制信号; 为0:计时功能; 为1:闹钟功能; 为2:手动校时功能; turn: 接按键,在手动校时功能时,选择是调整小时,还是分钟; 若长时间按住该键,还可使秒信号清零,用于精确调时; change: 接按键,手动调整时,每按一次,计数器加1; 如果长按,则连续快速加1,用于快速调时和定时; hour,min,sec:此三信号分别输出并显示时、分、秒信号, 皆采用BCD 码计数,分别驱动6 个数码管显示时间; alert: 输出到扬声器的信号,用于产生闹铃音和报时音; 闹铃音为持续20 秒的急促的“嘀嘀嘀”音,若按住“change”键, 则可屏蔽该音;整点报时音为“嘀嘀嘀嘀—嘟”四短一长音; LD_alert: 接发光二极管,指示是否设置了闹钟功能; LD_hour: 接发光二极管,指示当前调整的是小时信号; LD_min: 接发光二极管,指示当前调整的是分钟信号-err
Platform: | Size: 2048 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilogclock

Description: vhdl实现时钟和闹钟功能,此外还可以显示星期几,闹钟可以设置闹铃时间和报时。-implementation vhdl alarm clock and also can show a few weeks, you can set the alarm time and alarm time.
Platform: | Size: 748544 | Author: 季全 | Hits:

[VHDL-FPGA-VerilogDS1302

Description: 本代码是控制DS1302的VHDL代码,浅显易懂,方便修改,注意看data sheet,保证时钟和各个延迟满足要求即可-This code is to control the DS1302' s VHDL code, easy to understand, easy changes, note the data sheet, ensure the clock and can meet the requirements of the various delays
Platform: | Size: 2048 | Author: kaishi | Hits:

[VHDL-FPGA-VerilogDS1302

Description: 基于VerilogHDL编写的时钟管理芯片DS1302实验开发程序。-VerilogHDL prepared based on clock management chips DS1302 experimental development program.
Platform: | Size: 736256 | Author: sun pei | Hits:

[VHDL-FPGA-Verilogds1302

Description: 根据黑金动力编写的ds1302的vhdl程序,方便初学者对ds1302的学习-Ds1302 prepared according to the power of black gold vhdl procedures, easy for beginners to learn ds1302
Platform: | Size: 4096 | Author: fushenzhen | Hits:

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