Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder. Platform: |
Size: 154624 |
Author:凌音 |
Hits:
Description: 详细介绍双精度浮点数据的格式，以及加减乘除运算的实现方法-Details of the format of double-precision floating-point data, and the realization method of addition and subtraction multiplication and division Platform: |
Size: 96256 |
Author:小娟 |
Hits:
Description: 工具支持1、2、4、8字节整型、单精度浮点型、双精度浮点型、UNICODE以及ACSII字符搜索。搜索模式支持等于、大于、小于、两者之间、增大、减小、变化模式。另外还支持系列其他功能。
如今有很多内存修改器，功能也不乏强大的，但支持开源的不多。现将程序及源码附上，仅供需学习的同僚参考-The tool supports 1, 2, 4, 8-byte integer, single-precision floating-point, double-precision floating-point type, UNICODE, and ACSII character search. Search mode support is equal to, greater than, less than, between, increase, decrease, change mode. In addition to support for a series of other functions. Today a lot of memory to modify, there are some powerful functionality, but support for open source much. The program and source code are attached, colleagues need to learn only reference Platform: |
Size: 500736 |
Author:凌厉 |
Hits:
Description: 本文介绍用于计算IEEE 754标准的双精度64位浮点二进制数加/减法硬件架构。-In this article, an optimized pipeline
hardware architecture for computing IEEE 754 standard
double precision 64-bit floating point binary number
addition/subtraction was proposed. Platform: |
Size: 711680 |
Author:Jenny |
Hits:
Description: Floating Point FP multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex 6 FPGA. In addition, the proposed design is compliant with IEEE 754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices. Platform: |
Size: 52224 |
Author:kutti
|
Hits:
Search - double precision floating point addition